the PCI Bus demystified phần 8 docx

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Clock

2 The master deasserts LOCK# during the address phase.

This is how the locked target knows its being accessed by

the master owning the lock. Only the device asserting

LOCK# can release it.

3 and 4 The transaction proceeds normally.

5 If this is the last transaction in the locked series, the master

releases LOCK#.

PCI Bridging

Figure 8-16: Subsequent lock transactions.

If a locked target sees LOCK# asserted during the address phase,

a master other than the one owning the lock is attempting to access

the locked target (Figure 8-17). In this case the target executes a retry

abort.

Address

IRDY#

Data

CLK

FRAME#

AD

TRDY#

LOCK#

Release*

Continue

*Target unlocks when it detects FRAME# and LOCK# deasserted

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