the PCI Bus demystified phần 4 docx

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The Interrupt Acknowledge Command

Figure 4-2 illustrates the Interrupt Acknowledge command,

which is generated by the agent whose interrupt input is asserted.

In a typical single processor system this would be the main processor.

Only one agent in the system responds to the Interrupt Acknowledge

—typically the APIC.

Optional and Advanced Features

Figure 4-2: Interrupt Acknowledge command.

The AD bus is invalid during the address phase because the target

of the transaction, the APIC, recognizes it is being selected by virtue

of the Interrupt Acknowledge command. But again, the AD bus must

be driven to generate valid parity and prevent the receiver inputs

from floating.

The Interrupt Acknowledge cycle proceeds like any other PCI

cycle. The initiator asserts IRDY#. The interrupt controller asserts

DEVSEL# to claim the transaction and TRDY# when it is ready to

Not Valid

INT-ACK

IRDY#

BE#’s (1110)

CLK

FRAME#

AD

C/BE#

TRDY#

1 2 3 4 5

Vector

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supply the interrupt vector. The C/BE# bus indicates which bytes of

the interrupt vector are valid. Because PCI is processor independent,

we don’t necessarily know the nature or size of an interrupt vector.

That’s a function of the host processor architecture. The example

shows a typical x86 system where the interrupt vector is a single byte.

“Special” Cycle

The Special Cycle provides a mechanism to broadcast informa￾tion simultaneously to multiple targets. The specification suggests

that it is a useful way to convey sideband information to one or

more devices without the need for additional wires on the backplane.

One use for this facility is to broadcast processor status such as Halt

and Shutdown.

By definition, a Special Cycle is not directed at a specific target

but rather to any and all targets that have an interest in the message

being broadcast. This has several consequences:

■ The AD bus is not valid during the address phase. Of

course it must still be driven in order to generate parity

correctly.

■ Targets do not assert DEVSEL# or TRDY#.

■ Since DEVSEL# is not asserted, the only way for the

transaction to terminate is with a Master Abort.

During the data phase AD[15:0] conveys a predefined message

type. AD[31:16] may optionally carry message-dependent data.

Table 4-2 shows the currently defined messages.

Figure 4-3 shows the timing of a Special Cycle.

PCI Bus Demystified