the PCI Bus demystified phần 6 pdf

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master can retain ownership of the bus. Typically, the lower three bits

are hardwired to 0 and only the upper 5 bits are writable. This yields

a maximum of 255 clock cycles with a granularity of eight clock

cycles. The Latency Timer may be read-only if the master never

bursts more than two data phases.

Cache-Line Size

Configuration software writes the system cache line size in

DWORD increments to this register. It is required for any master

that implements the Memory Write and Invalidate command and for

any target that implements cache-line wrap addressing. Masters that

implement the advanced read commands should take advantage of

this register to optimize their use of the read commands.

Cardbus CIS Pointer

Optional. Implemented by devices that share silicon between

cardbus and PCI devices. It points to the Card Information Structure

for the Cardbus implementation. Details of the CIS can be found in

revision 3.0 of the PC Card specification.

Capabilities Pointer

If Status Register bit 4 = 1, this read-only byte is a pointer to the

first entry of the Capabilities List. It is a byte offset into the device￾specific configuration space.

Max_Lat (Maximum Latency)

The specification says that this optional register specifies “how

often the device needs to gain access to the PCI bus”. A better inter￾pretation might be how quickly the master needs access to the bus.

Values of Max_Lat are in increments of 250 ns which happens to be

about eight clocks at 33 MHz.

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The intention is that configuration software can use this value

to assign the master to an arbitration priority level. Devices with

lower values, implying a need for low latency, would be assigned to

the higher priority levels.

Min_Gnt (Minimum Grant)

This register indicates how long the master would like to retain

bus ownership when it initiates a transaction. Values of Min_Gnt are

in increments of 250 ns or eight clocks at 33 MHz.

Configuration software uses this value to set the device’s Latency

Timer.

Base Address Registers (BAR)

The Base Address Registers provide the mechanism that allows

configuration software to determine the memory and I/O resources

that a device requires. Once the system topology is determined,

configuration software maps all devices into a set of reasonable,

non-conflicting address ranges and writes the corresponding starting

addresses into the Base Address Registers. The Type 0 configuration

header supports up to six Base Address Registers, allowing a device

to have up to six independent address ranges.

There are two formats for the Base Register as shown in Figure

6-7. Read-only bit 0 determines whether the Base Address Register

represents memory or I/O space.

For memory space, read-only bits 1 and 2 indicate how the

memory space must be mapped and the size of the Base Address

Register. Memory can be mapped into either 32-bit or 64-bit address

space implying respectively a 32-bit register or a 64-bit register.

A 64-bit register occupies two adjacent BAR locations in the

Configuration Header. Prior to revision 2.2 the combination 01

Plug and Play Configuration