Tài liệu ARM Architecture Reference Manual- P18 ppt

Memory Management Unit

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. B3-9

3.3.5 Coarse page table descriptor

If the first-level descriptor is a coarse page table descriptor, the fields have the following meanings:

Bits[1:0] Identify the type of descriptor (0b01 marks a coarse page table descriptor).

Bits[4:2] The meaning of these bits is IMPLEMENTATION DEFINED.

Bits[8:5] The domain field specifies one of the sixteen possible domains for all the pages controlled

by this descriptor.

Bit[9] This bit is not currently used, and should be zero.

Bits[31:10] The Page Table Base Address is a pointer to a coarse second-level page table, giving the

base address for a second-level fetch to be performed. Coarse second-level page tables must

be aligned on a 1KB boundary.

If a coarse page table descriptor is returned from the first-level fetch, a second-level fetch is initiated to

retrieve a second-level descriptor, as shown in Figure 3-4.

Figure 3-4 Accessing coarse page table second-level descriptors

Translation

table base

Virtual

address

Address of

first-level descriptor

First-level descriptor

First-level fetch

31 14 13 0

Translation base 0 0

Translation base SBZ

Page table base address Domain IMP 0 1

Page table base address 0 0 Second-level

table index

31 14 1 13 2 0

First-level

table index

First-level

table index

Second-level

table index

31 20 19 0 12 11

Address of

second-level descriptor

31 9 0 8 5 4 2 1

31 9 0 2 1

10

10

S

B

Z

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Memory Management Unit

B3-10 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E

3.3.6 Fine page table descriptor

If the first-level descriptor is a fine page table descriptor, the fields have the following meanings:

Bits[1:0] Identify the type of descriptor (0b11 marks a fine page table descriptor).

Bits[4:2] The meaning of these bits is IMPLEMENTATION DEFINED.

Bits[8:5] The domain field specifies one of the sixteen possible domains for all the pages controlled

by this descriptor.

Bit[11:9] These bits are not currently used, and should be zero.

Bits[31:12] The Page Table Base Address is a pointer to a fine second-level page table, giving the base

address for a second-level fetch to be performed. Fine second-level page tables must be

aligned on a 4KB boundary.

If a fine page table descriptor is returned from the first-level fetch, a second-level fetch is initiated to retrieve

a second-level descriptor, as shown in Figure 3-5.

Figure 3-5 Accessing fine page table second-level descriptors

Translation

table base

Virtual

address

Address of

first-level descriptor

First-level descriptor

First-level fetch

31 14 13 0

Translation base 0 0

Translation base SBZ

Page table base address IMP Domain 1 1

Page table base address 0 0 Second-level

table index

31 14 1 13 2 0

First-level

table index

First-level

table index

31 20 19 0 10 9

Address of

second-level descriptor

31 8 5 4 2 1 0

31 11 0 12 2 1

SBZ

Second-level

table index

12 9 11

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Memory Management Unit

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. B3-11

3.3.7 Second-level descriptor

Each entry in a coarse second-level table corresponds to how a 4KB virtual address range is mapped, and

each entry in a fine second-level table corresponds to how a 1KB virtual address range is mapped. The

entries are page descriptors, and can describe a page which is larger than 4KB or 1KB respectively. When

this happens, the descriptor must be repeated enough times in the second-level table to ensure that the same

descriptor is always used for the page, regardless of which virtual address is being accessed within the page.

There are four possibilities for a second-level descriptor, selected by bits[1:0] of the descriptor as shown in

Table 3-2:

• If bits[1:0] == 0b00, the associated virtual addresses are unmapped, and attempts to access them

generate a translation fault (see Aborts on page B3-18). Software can use bits[31:2] for its own

purposes in such a descriptor, as they are ignored by the hardware. Where appropriate, it is suggested

that bits[31:2] continue to hold valid access permissions for the descriptor.

• If bits[1:0] == 0b01, the entry is a large page descriptor, describing 64KB of virtual addresses. See

Translating large page references on page B3-13 for details.

A large page descriptor must be repeated 64 times in a fine second-level table or 16 times in a coarse

second-level table to ensure that all of its virtual addresses are described.

• If bits[1:0] == 0b10, the entry is a small page descriptor, describing 4KB of virtual addresses. See

Translating small page references on page B3-14 for details.

A small page descriptor must be repeated four times in a fine second-level table to ensure that all of

its virtual addresses are described. In a coarse second-level table, only one instance of each small

page descriptor is needed.

• If bits[1:0] == 0b11, the entry is a tiny page descriptor, describing 1KB of virtual addresses. See

Translating tiny page references on page B3-15 for details.

Only one instance of each tiny page descriptor is needed in a fine second-level table. Tiny page

descriptors must not appear in coarse second-level tables. If they do, the results are UNPREDICTABLE.

Table 3-2 Second-level descriptor format

31 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0

Fault IGN 0 0

Large page Large table base address SBZ AP3 AP2 AP1 AP0 C B 0 1

Small page Small page base address AP3 AP2 AP1 AP0 C B 1 0

Tiny page Tiny page base address SBZ AP C B 1 1

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