Tài liệu ARM Architecture Reference Manual- P15 ppt

The 26-bit Architectures

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A8-11

26-bit configuration

1. If PROG32 is not active, the processor is locked into 26-bit modes (that is, cannot be placed into a

32-bit mode by any means) and handles exceptions in 26-bit modes. This is called a 26-bit

configuration. In this configuration, CMNP, CMPP, TEQP and TSTP instructions, or the MSR

instruction can be used to switch to 26-bit modes. Attempts to write CPSR bits[4:2] (M[4:2]) are

ignored, stopping any attempts to switch to a 32-bit mode, and SVC_26 mode is used to handle

memory aborts and Undefined Instruction exceptions. The PC is limited to 24 bits, limiting the

addressable program memory to 64MB.

2. If PROG32 is not active, DATA32 has the following actions:

• If DATA32 is not active, all data addresses are checked to ensure that they are between 0 and

64MB. If a data address is produced with a 1 in any of the top 6 bits, an address exception is

generated.

• If DATA32 is active, full 32-bit addresses can be produced and are not checked for address

exceptions. This allows 26-bit programs to access data in the full 32-bit address space.

8.5.2 Vector exceptions

When the processor is in a 32-bit configuration (PROG32 is active) and in a 26-bit mode (CPSR[4] == 0),

data access (but not instruction fetches) to the exception vectors (address 0x0 to 0x1F) causes a data abort.

This is known as a vector exception.

Vector exceptions are always produced if the exception vectors are written in a 32-bit configuration and a

26-bit mode. It is IMPLEMENTATION DEFINED whether reading the exception vectors in a 32-bit

configuration and a 26-bit mode also causes a vector exception.

Vector exceptions are provided to support 26-bit backwards compatibility. When a vector exception is

generated, it indicates that a 26-bit mode process is trying to install a (26-bit) vector handler. Because the

processor is in a 32-bit configuration, exceptions are handled in a 32-bit mode, so a veneer must be used to

change from the 32-bit exception mode to a 26-bit mode before calling the 26-bit exception handler.

This veneer can be installed on each vector and can switch to a 26-bit mode before calling any 26-bit

handlers.

The return from the 26-bit exception handler might also need to be veneered. Some SWI handlers return

status information in the processor flags, and this information needs to be transferred from the link register

to the SPSR with a return veneer for the SWI handler.

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The 26-bit Architectures

A8-12 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E

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ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A9-1

Chapter A9

ARM Code Sequences

The ARM instruction set is a powerful tool for generating high-performance microprocessor systems. Used

to its full extent, the ARM instruction set allows algorithms to be coded in a very compact and efficient way.

This chapter describes some sample routines that provide insight into the ARM instruction set. It contains

the following sections:

• Arithmetic instructions on page A9-2

• Branch instructions on page A9-5

• Load and Store instructions on page A9-7

• Load and Store Multiple instructions on page A9-10

• Semaphore instructions on page A9-11

• Other code examples on page A9-12.

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