Tài liệu ARM Architecture Reference Manual- P17 doc

Introduction to Memory and System Architectures

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. B1-3

Note

Because of the wide variety of systems based on ARM processors, all functionality described in Part B

might be inappropriate to any given system. Furthermore, some ARM processors have implemented

functions in a different manner to the one described here. Because of this, the datasheet or Technical

Reference Manual for a particular ARM processor is the definitive source for its memory and system control

facilities.

Part B therefore does not attempt to specify absolute requirements on the functionality of the System

Control coprocessor or other memory system components. Instead, it contains guidelines which, if

followed:

• mean that the system is more likely to be compatible with existing and future ARM software.

• probably make it easier to port incompatible software to the system.

In order to provide an adequate description of the range of memory and system facilities on existing ARM

implementations, Part B describes a number of options that will not be used on new ARM implementations.

For information on the rules that must be followed by new implementations of the memory and system

architectures, contact ARM Ltd.

The fact that Part B describes a broad range of facilities, many of which are used only on some existing

ARM implementations, also means that architecture version numbers for the memory and system

architectures would not be helpful or descriptive. They are therefore not used.

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Introduction to Memory and System Architectures

B1-4 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E

1.2 System-level issues

This section lists a number of general and operating-system issues that the system designer needs to address

when using an ARM processor.

1.2.1 Memory systems, write buffers and caches

ARM processors and software are designed to be connected to a byte-addressed memory. Word and

halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value

that is addressed (so a memory access ignores address bits 0 and 1 for word access, and ignores bit 0 for

halfword accesses). The endianness of the ARM processor should normally match that of the memory

system, or be configured to match it before any non-word accesses occur (when the endianness is

configurable and CP15 is implemented, bit[7] of CP15 register 1 controls the endianness).

Memory that is used to hold programs and data should be marked as follows:

• Main (RAM) memory is normally set as cachable and bufferable.

• ROM memory is normally set as cachable, and should be marked as read only, so the bufferable

attribute is not used and should be 1.

Write buffers

Some ARM implementations incorporate a merging write buffer that subsumes multiple writes to the same

location into a single write to main memory. Furthermore, some write buffers re-order writes, so that writes

are issued to memory in a different order to the order in which they are issued by the processor. Therefore,

I/O locations should not normally be marked as bufferable, to ensure all writes are issued to the I/O device

in the correct order.

For writes to bufferable areas of memory, memory aborts can only be signaled to the processor as a result

of conditions that are detectable at the time the data is placed in the write buffer. Conditions that can only

be detected when the data is later written to main memory (such as a parity error from main memory) must

be handled by other methods (typically by raising an interrupt).

Caches

Frame buffers can be cachable, but frame buffers on writeback cache implementations must be copied back

to memory after the frame buffer has been updated. Frame buffers can be bufferable, but again the write

buffer must be written back to memory after the frame buffer has been updated.

ARM processors do not normally support cache coherence between the ARM and other system bus masters.

Bus snooping is not supported. If memory data is to be shared between multiple bus masters without taking

special software measures to ensure coherency, then the data must be mapped as:

• uncachable to ensure that all reads access main memory

• unbufferable to ensure that all write access main memory.

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Introduction to Memory and System Architectures

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. B1-5

Alternatively, using software, you can manage the coherence of data buffers that are read or written by

another bus master by:

• cleaning data from writeback caches and write buffers to memory when the processor has written to

the data buffer and before the other bus master reads the buffer

• flushing relevant data from caches when the buffer is being read after the other bus master has written

the buffer.

You can use an uncached, unbuffered semaphore to maintain synchronization between multiple bus masters

(see Semaphores on page B1-6).

For implementations with writeback caches, all dirty cache data must be written back before any alterations

are made to the MMU page tables, to ensure that cache line write back can use the page tables to form the

correct physical address for the transfer.

You can index caches using either virtual or physical addresses. Physical pages must only be mapped into

a single virtual page, otherwise the result is UNPREDICTABLE. ARM processors do not normally provide

coherence between multiple virtual copies of a single physical page.

Some ARM implementations support separate instruction and data caches. Coherence between the data and

instruction caches is not necessarily maintained in hardware, so if the instruction stream is written, the

instruction cache and data cache must be made coherent. This can entail:

• cleaning the data cache (storing dirty data to memory)

• draining the write buffer (completing all buffered writes)

• flushing the instruction cache.

Instruction and data memory incoherence occurs after a program has been loaded (and therefore treated as

data) and is about to be executed. It also occurs if self-modifying code is used or generated.

1.2.2 Interrupts

ARM processors implement fast and normal levels of interrupt. Both interrupts are signaled externally, and

many implementations synchronize interrupts before an exception is raised.

Fast interrupt request (FIQ)

Disables subsequent normal and fast interrupts by setting the I and F bits in the CPSR.

Normal interrupt request (IRQ)

Disables subsequent normal interrupts by setting the I bit in the CPSR.

For more information, see Exceptions on page A2-13.

Canceling interrupts

It is the responsibility of software (the interrupt handler) to ensure that the cause of an interrupt is canceled

(no longer signaled to the processor) before interrupts are re-enabled (by clearing the I and/or F bit in the

CPSR). Interrupts can be canceled with any instruction that might make an external data bus access,

meaning any load or store, a swap, or any coprocessor instruction.

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