Tài liệu ARM Architecture Reference Manual- P16 ppt

Enhanced DSP Extension

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A10-11

Usage

MCRR is used to initiate coprocessor operations that depend on values in two ARM registers. An example

for a floating-point coprocessor is an instruction to transfer a double-precision floating-point number held

in two ARM registers to a floating-point register.

Notes

Coprocessor fields

Only instruction bits[31:8] are defined by the ARM architecture. The remaining fields are

recommendations, for compatibility with ARM Development Systems.

Unimplemented coprocessor instructions

Hardware coprocessor support is optional, regardless of the architecture version. An

implementation may choose to implement a subset of the coprocessor instructions, or no

coprocessor instructions at all. Any coprocessor instructions that are not implemented

instead cause an undefined instruction trap.

Order of transfers

If a coprocessor uses these instructions, it will define how each of the values of <Rd> and

<Rn> is used. There is no architectural requirement for the two register transfers to occur

in any particular time order. It is IMPLEMENTATION DEFINED whether Rd is transferred

before Rn, after Rn, or at the same time as Rn.

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Enhanced DSP Extension

A10-12 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E

10.6.3 MRRC

The MRRC instruction causes the coprocessor whose number is cp_num to transfer values to two ARM

registers <Rd> and <Rn>. If no coprocessors indicate that they can execute the instruction, an undefined

instruction exception is generated.

Syntax

MRRC{<cond>} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>

where:

<cond> Is the condition under which the instruction is executed. The conditions are defined in The

condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<coproc> Specifies the name of the coprocessor, and causes the corresponding coprocessor number to

be placed in the cp_num field of the instruction. The standard generic coprocessor names

are p0, p1, …, p15.

<opcode> Is a coprocessor-specific opcode.

<Rd> Is the first destination ARM register. If R15 is specified for <Rd>, the result is

UNPREDICTABLE.

<Rn> Is the second destination ARM register. If R15 is specified for <Rn>, the result is

UNPREDICTABLE.

<CRm> Is the coprocessor register which supplies the data to be transferred.

Architecture version

E variants of version 5 and above, excluding ARMv5TExP

Exceptions

Undefined instruction

Operation

if ConditionPassed(cond) then

Rd = first value from Coprocessor[cp_num]

Rn = second value from Coprocessor[cp_num]

31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 4 3 0

cond 1 1 0 0 0 1 0 1 Rn Rd cp_num opcode CRm

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Enhanced DSP Extension

ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A10-13

Usage

MRRC is used to initiate coprocessor operations that write values to two ARM registers. An example for a

floating-point coprocessor is an instruction to transfer a double-precision floating-point number held in a

floating-point register to two ARM registers.

Notes

Operand restrictions

Specifying the same register for <Rd> and <Rn> has UNPREDICTABLE results.

Coprocessor fields

Only instruction bits[31:8] are defined by the ARM architecture. The remaining fields are

recommendations, for compatibility with ARM Development Systems.

Unimplemented coprocessor instructions

Hardware coprocessor support is optional, regardless of the architecture version. An

implementation may choose to implement a subset of the coprocessor instructions, or no

coprocessor instructions at all. Any coprocessor instructions that are not implemented

instead cause an undefined instruction trap.

Order of transfers

If a coprocessor uses these instructions, it will define which value is written to <Rd> and

which value to <Rn>. There is no architectural requirement for the two register transfers to

occur in any particular time order. It is IMPLEMENTATION DEFINED whether Rd is transferred

before Rn, after Rn, or at the same time as Rn.

Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.