Adaptive Techniques for Dynamic Processor Optimization Theory and Practice Episode 2 Part 8 pot

Chapter 12 The Challenges of Testing Adaptive Designs 293

During wafer sort, where bare die is tested, the on-package band-gap

reference is not available and the band-gap reference is replaced by a fixed

voltage. Firmware is loaded into the microcontroller to evaluate the

linearity and gain of the voltage/VCO count table. In Figure 12.13, this

process is shown using both a good and a bad part.

Figure 12.13 Process for evaluating VCO table.

For the bad part, an increase in voltage from 1.007 to 1.015 caused a

decrease in VCO count from 21391 to 21389. This behavior would cause

the count 21390 to make to both 1.011V and 1.006V making voltage

measurement far too inaccurate to measure power accurately.

With the testing of the VCO complete, the on-package parasitic

resistance can be measured. If the resistance is too low, not enough

voltage delta will be generated under load to get an accurate power

measurement. If the resistance is too high, significant power is wasted in

the package itself.

By measuring the voltage drop across the connector (Vc1–Vd1) using the

VCO while the chip is idle and consuming standby current I0 and then

measuring the voltage drop (Vc2–Vd2) while the chip is under a known

additional current load, IDelta, the package resistance can be computed using

a simple formula (Figure 12.14). This formula, once again, is applied

using special firmware in the microcontroller and the range is tested to be

within acceptable limits (Figure 12.15).