Adaptive Techniques for Dynamic Processor Optimization Theory and Practice Episode 2 Part 6 ppt

Chapter 11 Dynamic and Adaptive Techniques in SRAM Design 253

2nd Metal

#WE

WE[n] WE[n+1]

4th Metal

n_arvdd n+1_arvdd

downvdd

n_Bit n_#Bit n+1_Bit n+1_#Bit

Capacitive Write

Assist Circuit

WL

WL

P-Tr[n]

N-Tr[n]

P-Tr[n+1]

N-Tr[n+1]

Nd-Tr

Figure 11.4 Charge sharing for supply reduction [14]. (© 2007 IEEE)

Since extra supplies are not always available in product design, another

example [14] uses charge sharing to lower the supply to the columns being

written to. As shown in Figure 11.4, “downvdd” is precharged to VSS.

For a write operation, supplies to the selected columns are disconnected

from VDD, and shorted to “downvdd”. The charge sharing lowers the

supply’s voltage to a level determined by the ratio of the capacitances,

allowing writes to occur easily.

254 John J. Wuu

Memory cell

Memory cell Memory cell

Memory cell

Vssm

Vdd

Vddm[n]

Vddm[n+1]

WCLM[n] WCLM[n+1]

MSW[n] MSW[n+1]

Figure 11.5 Write column supply switch off [21]. (© IEEE 2006)

Yet another example [21] uses a power-line-floating write technique to

assist write operations. Instead of switching in a separate supply or charge

sharing the supply, as in previous examples, the supply to the write columns is

simply switched off, floating the column supply lines at VDD (Figure 11.5).

As the cells are written to, the floating supply line (Vddm) discharges

through the “0” bitline, as shown in Figure 11.6a. The decreased supply

voltage allows easy writing to the cells. As soon as the cell flips to its

intended state, the floating supply line’s discharge path is cut off, preventing

the floating supply line from fully discharging (Figure 11.6b).

Iwrite

“L”

“L”

“H”

“H”

Vddm

Vddm

“L” “H”

“L” “H”

(a) (b)

Figure 11.6 Power-line-floating write [21]. (© IEEE 2006)