Adaptive Techniques for Dynamic Processor Optimization_Theory and Practice Episode 2 Part 2 pdf

170 Alan Drake

microprocessor. This monitor has a 12-bit thermometer-code output. One

advantage of a thermometer-code output is the ability to quantify noise

processes in test and debug, as well as during operation. This monitor pro￾vides a sampling function as well as maintaining the worst-case delay

since it was last read.

Table 7.1 Comparison chart of different critical path monitors in the literature.

Column order is by date of publication.

[10] [9] [14] [24] [2]

Application 16×16

multi￾plier

IBM

POWER6

Intel

Montecito

MPEG4

decoder

64-bit

alpha

Synchronizer Flip-flop Flip-flop Finite state

machine

Pulse

generator

Flip-flop

or Razor

latch

Delay path One

serial

path

Five paral￾lel paths

Two syn￾thesis

paths: each

has two

serial paths

in parallel

1 serial

path

Embed￾ded into

actual

critical

path

Time-to￾digital con￾version

Flip￾flop: 1

bit

Flip-flop:

12-bit

thermome￾ter code

Multiplex￾ing latch: 2

bits

Flip-flop:

n-bit ther￾mometer

code

Razor

latch: 1

bit

Monitor

density

1 8/core 12/core 1/chip 192/chip

Technology 0.18

μm

65 nm 90 nm 0.18 μm 0.18 μm

Approximate

area

1

>1000

flip￾flops

215 flip￾flops

> 100 flip￾flops

>100

flip-flops

2–3 flip￾flops

Target

Frequency

90

MHz

4–5 GHz 2–2.5 GHz 8–123

MHz

200

MHz

1 The monitor area is the approximate area as a multiple of the area of a single

flip-flop, not the number of flip-flops in the monitor. This metric is used to allow

comparisons to be made independently of technology. Target frequency has a

large impact on area as it impacts the length of the delay lines used to synthesize

the critical path. Area is based on published descriptions and, except for [9], does

not include configuration, control, and test logic not described.

Chapter 7 Sensors for Critical Path Monitoring 171

The critical path monitor in [10] has a clever self-calibrating scheme

that adjusts the critical path settings based on the output of a process sensi￾tive ring oscillator. This monitor is very large and could not be widely dis￾tributed around an integrated circuit without significant area penalties.

Voltage and temperature sensitivity are increasing with process scaling,

making processor timing very susceptible to workload. Because workload

is a systematic noise, critical path monitors allow DVFS systems (which

have begun to multiply in recent years) to respond to the workload and im￾prove the efficiency of the microprocessors. These circuits tend to be

small, having the same area of roughly 100–200 flip-flops. They can be

made sensitive to voltage, process, temperature, aging, NBTI, and work￾load while allowing the system to respond and adapt to these noise proc￾esses. Critical path monitors have been reported to be sensitive to changes

in delay as small as an FO2 inverter delay ([14] showed a sensitivity of

1.5% of a clock period). In addition to providing accurate timing meas￾urements, critical path monitors can be valuable tools in testing and de￾bugging new integrated circuit designs. In order to make a critical path

monitor worthwhile, it must provide enough accuracy to reduce the design

margins allocated for environmental changes in the integrated circuit.

Acknowledgments

The contribution made by each of the following individuals is gratefully

acknowledged: Robert Senger, Harmander Deogun, Gary Carpenter, Tuyet

Nguyen, Jeremy Schaub, Soraya Ghiasi, Norman James, Michael Floyd,

Phillip Restle, Scott Taylor, Kevin Nowka, Sani Nassif, Fadi Gebara,

Robert Montoye, and Hung Ngo. Funding was provided in part under

DARPA contract number NBCH30390004.

References

[1] K. Agarwal and S. Nassif, “Characterizing Process Variation in Nanometer

CMOS,” DAC, 4–8 June 2007, pp. 396–399.

[2] T. Austin, D. Blaauw, T. Mudge, and K. Flautner, “Making Typical Silicon

Matter with Razor,” Computer, vol. 27, no. 3, Mar 2004, pp. 57–65.

[3] J. Blome, S. Feng, S. Gupta, and S. Mahlke, “Self-Calibrating Online Wear￾out Detection,” MICRO, 1–5 Dec 2007.

[4] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De,

“Parameter Variations and Impact on Circuits and Microarchitecture,” DAC,

2–6 June 2003, pp. 338–342.