Adaptive Techniques for Dynamic Processor Optimization_Theory and Practice Episode 2 Part 1 potx

150 Alan Drake

approximately equal. A critical path monitor located near high-power den￾sity circuits will track the temperature-induced timing changes of those cir￾cuits. The number of sensors is determined by the number of regions of

high-power density on the integrated circuit.

Supply voltage [19], [31] variation has a much shorter time constant.

The initial depth of a voltage droop, ΔV, is determined by the effective de￾coupling capacitance, Cdc, and the amount of current drawn, I, over a time

period, Δt, as given by

Cdc

I t V Δ Δ = . (7.3)

The duration of the voltage droop is a function of the RLC characteristics

of the power supply network and its ability to provide enough current to

boost the power supply backup to its nominal value. In integrated circuits

where decoupling capacitance is insufficient, but a robust power supply

distribution exists, voltage droops will be large, but short lived. Adding

additional decoupling capacitance will slow down and reduce the ampli￾tude of voltage droops.

In a 65nm, dual-core processor designed to test the performance of the

power supply distribution, large changes in the number of registers used

in each cycle resulted in voltage droops around 150mV that lasted sev￾eral nanoseconds. A voltage droop caused by activity changes in one core

traveled to the second core on-chip in around 4ns where it was attenuated

by the capacitive load of the second core. A large droop in both cores at

simultaneous moments caused a large drop in the overall supply

voltage [19].

Because power supply droop travels from where the current draw is

highest to other parts of the integrated circuit, relatively few critical path

monitors are needed to detect them, as even a single critical path monitor

will eventually see the attenuated supply droop. Of more importance is

how soon after its occurrence the droop needs to be detected. In DVFS

systems that track the supply noise, more critical path monitors will be

needed, and they will need to be located close to the circuits most respon￾sible for dynamic current draw. For slower systems, fewer monitors are

needed.

Clock jitter and skew are largely dependent on the power supply noise. The

value of each of these noise processes depends on the stability of the switching

points of the logic gates in the clock distribution and in the logic paths. As

power supply noise increases, the switching point of the logic gates

changes, injecting the power supply noise into the clock distribution [8].

Chapter 7 Sensors for Critical Path Monitoring 151

Aging [3] and NBTI [12] have long time constants, but their spatial con￾stant can be quite small. General aging across a chip will be tracked by a

single critical path monitor, but some aging processes may affect a single

transistor. The best response to tracking these types of changes in timing is

to locate the critical path monitors close to the most active circuitry, which

sees the widest swing in environmental conditions.

7.4 Timing Sensitivity of Path Delay

In order to build an effective critical path monitor, it is essential to under￾stand the sensitivity of path delay to noise. The typical logic path begins at

a latch and ends at a latch: on receipt of a clock signal, the data is passed

through the logic from the source latch to the final latch. SRAM critical

paths are more complicated than logic paths because the control signal of￾ten crosses supply voltage boundaries and interfaces with analog sense￾amps. Because of this, we will ignore the intricacies of SRAM and just

deal with the timing of regular logic.

Figure 7.3 shows a simplified model of a critical path consisting of logic

elements driving equal lengths of wire [17]. Most any logic path can be re￾duced, to the first order, to a buffer-driven delay-line model by converting

any gate with multiple fan-in to an equivalent inverter. The wire length of

each segment is adjusted to match the wire length between gates. Fan-out

is added as additional gate capacitance load at a given stage. While these

modifications can tailor the model in Figure 7.3 to most any logic path, for

this analysis, it is simpler and sufficient to analyze the path as a simple

buffered delay line.

















 

 

      

Figure 7.3 A simplified model of a delay line based on the theory developed in [17].

Placing sufficient critical monitors to track power supply noise should also

capture clock jitter and skew.