Adaptive Techniques for Dynamic Processor Optimization Theory and Practice Episode 2 Part 7 potx

Chapter 12 The Challenges of Testing Adaptive

Designs

Eric Fetzer, Jason Stinson, Brian Cherkauer, Steve Poehlman

Intel Corporation

In this chapter, we describe the adaptive techniques used in the Itanium® 2

9000 series microprocessor previously known as Montecito [1].

Montecito features two dual-threaded cores with over 26.5 MB of total

on die cache in a 90nm process technology [2] with seven layers of copper

interconnect. The die, shown in Figure 12.1, is 596 mm2

in size, contains

1.72 billion transistors, and consumes 104 W at a maximum frequency of

1.6 GHz. To manufacture a product of such complexity, a sophisticated

series of tests are performed on each part to ensure reliable operation

throughout its service at a customer installation. Adaptive features often

interfere with these tests. This chapter discusses three adaptive features

on Montecito: active de-skew for reliable low skew clocks, Cache Safe

Technology® for robust cache operation, and Foxton Technology® for

power management. Traditional test methods are discussed, and the

specific impacts of active de-skew and the power measurement system for

Foxton are highlighted. Finally, we analyze different power management

systems and consider their impacts on manufacturing.

12.1 The Adaptive Features of the Itanium 2 9000 Series

12.1.1 Active De-skew

The large die of the Montecito design results in major challenges in

delivering a low skew global clock to all of the clocked elements on the

die. Unintended clock skew directly impacts the frequency of the design

by shortening the sample edge of the clock relative to the driving edge

of a different clock. Random and systematic process variation in both the

A. Wang, S. Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization,

DOI: 10.1007/978-0-387-76472-6_12, © Springer Science+Business Media, LLC 2008

274 Eric Fetzer, Jason Stinson, Brian Cherkauer, Steve Poehlman

Figure 12.1 Montecito die micrograph.

transistor and metal layers makes it difficult to accurately design a static

clock distribution network that will deliver a predictable clock edge

placement throughout the die. Additionally, dynamic runtime effects such

as local voltage droop, thermal gradients, and transistor aging further add

to the complexity of delivering a low skew clock network. As a result of

these challenges, the Montecito design implemented an adaptive de￾skewing technique to significantly reduce the clock skew while keeping

power consumption to a minimum.

21.5 mm

27.7 mm

Traditional methods of designing a static low skew network include

both balanced Tree and Grid approaches (Figure 12.2). The traditional

Tree network uses matching buffer stages and either layout-identical metal

routing stages (each route has identical length/width/spacing) or delay￾identical metal routing (routes have different length/width/spacing but

same delay). A Grid network also uses matched buffer stages but creates a

shorted “grid” for the metal routing, where all the outputs of a particular

clock stage are shorted together.