Adaptive Techniques for Dynamic Processor Optimization_Theory and Practice Episode 1 Part 7 ppsx

Chapter 5 Adaptive Supply Voltage Delivery for U-DVS Systems 109

5.3.2 DC–DC Converter Topologies for U-DVS

5.3.2.1 Linear Regulators

Low-dropout (LDO) linear regulators [22] are widely used to supply ana￾log and digital circuits and feature in several standalone or embedded

power management ICs. The main advantage of LDO’s is that they can be

completely on-chip, occupy very little area, and offer good transient and

ripple characteristics, together with being a low-cost solution. Using

LDO’s for U-DVS, however, is detrimental because of the linear loss of

efficiency in an LDO. A linear regulator essentially controls the resistance

of a transistor in order to regulate the output voltage. As a result, the cur￾rent delivered to the load flows directly from the battery and hence the

maximum efficiency achievable is limited to the ratio of the output voltage

to the input voltage. Thus, the farther away the load voltage is from the

battery voltage, the lower the efficiency of the LDO. This hampers the po￾tential savings in power consumption that can be achieved by lowering the

voltage through DVS.

5.3.2.2 Inductor-Based DC–DC Converter

The most efficient DC–DC voltage converters are inductor-based switch￾ing regulators, which normally generate a reduced DC voltage level by fil￾tering a pulse-width modulated (PWM) signal through a simple LC filter.

A buck-type regulator can generate different DC voltage levels by varying

the duty-cycle of the PWM signal. Given ideal devices and passives, an

inductor-based DC–DC converter can theoretically achieve 100% effi￾ciency independent of the load voltage being delivered. Moreover, in the

context of DVS systems, scaling the output voltage can be done with com￾pletely digital control circuitry [21] which consumes very little overhead

power. An implementation of an inductor-based switching regulator for

minimum energy operation is described in Section 5.3.3.1C. While buck

converters [23] can operate at very high efficiencies (>90%), they gener￾ally require off-chip filter components. This might limit their usefulness

for integrated power converter applications. Integrating the filter inductor

on-chip requires very high switching frequencies (>100MHz) in order to

minimize area consumed. This increases the switching losses in the con￾verter and together with the increase in conduction losses due to the low

inductor Q-factors achievable on-chip severely affects the efficiency that

can be obtained out of the converter.

110 Yogesh K. Ramadass, Joyce Kwong, Naveen Verma, Anantha Chandrakasan

5.3.2.3 Switched Capacitor-Based DC–DC Converter

U-DVS systems often require multiple on-chip voltage domains with each

domain having specific power requirements. A switched capacitor (SC)

DC–DC converter is a good choice for such battery-operated systems be￾cause it can minimize the number of off-chip components and does not re￾quire any inductors. Previous implementations of SC converters (charge

pumps) have commonly used off-chip charge-transfer capacitors [24] to

output high load power levels. A SC DC–DC converter which integrates

the charge-transfer capacitors was described in [25].

Cload IO

VO = VNL − ΔV

C

C

VBAT

Φ1 Φ2

Φ2

Φ1 Φ2 Cload IO

VO = VNL − ΔV

C

C

VBAT

Φ1 Φ2

Φ2

Φ1 Φ2

Figure 5.13 A switched capacitor voltage divide-by-2 circuit.

Consider the divide-by-2 circuit shown in Figure 5.13. The charge￾transfer (flying) capacitors are equal in value and help in transferring

charge from the battery to the load. During phase Φ1 of the system clock,

the charge-transfer capacitors get charged from the battery (VBAT). In the

Φ2 phase of the clock, they dump the charge gained onto the load. At no

load, this circuit tries to maintain the output voltage VO at VBAT/2, where

VBAT is the battery voltage. The actual value of VO that the circuit settles

down to is dependent on the load current IO, the switching frequency, and

C. Let the circuit deliver a load voltage VO = VNL – ΔV, where VNL is the

no-load voltage for this topology. The SC converter limits the maximum

efficiency that can be achieved in this case to ηlin = (1 – ΔV/VNL). Thus,

the farther away VO is from VNL (i.e., higher ΔV), the smaller the maxi￾mum efficiency that can be achieved by this topology. This is a fundamen￾tal problem with charge transfer using only capacitors and switches. The

linear efficiency loss is similar to linear regulators. However, with SC

converters, it is possible to switch in different gain-settings whose no-load