Examples of VHDL Descriptions phần 6 pptx

Examples of VHDL Descriptions

WAIT FOR 20 us;

END PROCESS control_waves;

END block_struct;

Sinewave generator for testbench

--entity to generate a 2.5kHz sampled sinewave (sampled at 20 us intervals)

USE WORK.adcpac.ALL;

ENTITY sinegen IS

PORT(sinewave : OUT analogue);

END sinegen;

ARCHITECTURE behaviour OF sinegen IS

CONSTANT ts : TIME := 20 us; --sample interval

TYPE sinevals IS ARRAY (0 TO 5) OF analogue;

--sample values for one quarter period

CONSTANT qrtrsine : sinevals := (0.0, 1.545, 2.939, 4.045, 4.755, 5.0);

BEGIN

PROCESS --sequential process generates sinewave

BEGIN

FOR i IN 0 TO 19 LOOP --output 20 samples per period

IF (i >= 0) AND (i < 6) THEN --first quarter period

sinewave <= qrtrsine(i);

ELSIF (i >= 6) AND (i < 11) THEN --second quarter period

sinewave <= qrtrsine(10-i);

ELSIF (i >= 11) AND (i < 16) THEN --third quarter period

sinewave <= -qrtrsine(i-10);

ELSE --i IN 16 TO 19

sinewave <= -qrtrsine(20-i); --final quater period

END IF;

WAIT FOR ts;

END LOOP;

END PROCESS;

END behaviour;

Testbench for Digital Delay Unit

USE WORK.rampac.ALL;

USE WORK.adcpac.ALL;

ENTITY delay_bench IS

PORT(reset : IN BIT; delay : IN addr10);

END delay_bench;

ARCHITECTURE version1 OF delay_bench IS

COMPONENT sinegen

PORT(sinewave : OUT analogue);

END COMPONENT;

COMPONENT digdel2

PORT(clear : IN BIT; offset : IN addr10;

sigin : IN analogue; sigout : INOUT analogue);

END COMPONENT;

SIGNAL analogue_in, analogue_out : analogue;

BEGIN

sig_gen : sinegen PORT MAP(analogue_in);

delay_unit : digdel2 PORT MAP(reset, delay, analogue_in, analogue_out);

￾h￾t￾t￾p￾:￾/￾/￾w￾w￾w￾.￾a￾m￾i￾.￾b￾o￾l￾t￾o￾n￾.￾a￾c￾.￾u￾k￾/￾c￾o￾u￾r￾s￾e￾w￾a￾r￾e￾/￾a￾d￾v￾e￾d￾a￾/￾v￾h