Examples of VHDL Descriptions phần 3 pdf

Examples of VHDL Descriptions

clock <= '0', '1' after 50 ms;

wait for 100 ms;

end process;

--test inputs

process begin

pedestrian <= '0';

reset <= '1';

wait for 300 ms;

reset <= '0';

wait for 40000 ms;

pedestrian <= '1';

wait for 200 ms;

pedestrian <= '0';

wait;

end process;

pelican : pelcross port map (clock, reset, pedestrian,

red, amber, green);

end v1;

Simple Microprocessor System

● Package Defining the Instruction Set of the CPU

● Third Party Package containing functions for Bit_Vector operations

● Behavioural model of a 256-word, 8-bit Read Only Memory

● Behavioural model of a 16-word, 8-bit Random Access Memory

● Behavioural model of a simple 8-bit CPU

● Structural description of a microprocessor system using the above components

Package Defining the Instruction Set of the CPU

PACKAGE cpu8pac IS

--defining instruction set

--instruction format

-- 7----4|3--0|7----------0

-- opcode|page|[page offset]

--instructions which need an address are two bytes

--long all others are single byte

CONSTANT lda : BIT_VECTOR(3 DOWNTO 0) := "0001";

CONSTANT ldb : BIT_VECTOR(3 DOWNTO 0) := "0010";

CONSTANT sta : BIT_VECTOR(3 DOWNTO 0) := "0011";

CONSTANT stb : BIT_VECTOR(3 DOWNTO 0) := "0000";

CONSTANT jmp : BIT_VECTOR(3 DOWNTO 0) := "0100";

CONSTANT add : BIT_VECTOR(3 DOWNTO 0) := "0101";

CONSTANT subr : BIT_VECTOR(3 DOWNTO 0) := "0110";

CONSTANT inc : BIT_VECTOR(3 DOWNTO 0) := "0111";

CONSTANT dec : BIT_VECTOR(3 DOWNTO 0) := "1000";

CONSTANT land : BIT_VECTOR(3 DOWNTO 0) := "1001";

CONSTANT lor : BIT_VECTOR(3 DOWNTO 0) := "1010";

CONSTANT cmp : BIT_VECTOR(3 DOWNTO 0) := "1011";

CONSTANT lxor : BIT_VECTOR(3 DOWNTO 0) := "1100";

CONSTANT lita : BIT_VECTOR(3 DOWNTO 0) := "1101";

CONSTANT litb : BIT_VECTOR(3 DOWNTO 0) := "1110";

CONSTANT clra : BIT_VECTOR(3 DOWNTO 0) := "1111";

END cpu8pac;

Third Party Package containing functions for Bit_Vector operations

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