Examples of VHDL Descriptions phần 4 pdf

Examples of VHDL Descriptions

end process;

end architecture v1;

Controller

--controller for lottery number generator

--new version uses 6 number registers and

--compares all numbers simulateously

library ieee;

use ieee.std_logic_1164.all;

entity lottcont2 is

port(clock, reset, next_no, match : in std_logic;

loadnum1, loadnum2, loadnum3, loadnum4,

loadnum5, loadnum6, sample : out std_logic;

seldisplay : out natural range 0 to 5;

numled : out std_logic_vector(1 to 6));

end entity lottcont2;

architecture fsm2 of lottcont2 is

type lott_state_type is (res, s1, s2, s3, s4, s5, s6, s7,

s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18,

s19, s20, s21, s22, s23, s24, s25, s26, s27, s28);

signal lott_ps, lott_ns : lott_state_type;

begin

--next state process

fsm_state_reg : process

begin

wait until rising_edge(clock);

if reset = '1' then

lott_ps <= res;

else

lott_ps <= lott_ns;

end if;

end process;

fsm_logic : process(lott_ps, next_no, match)

begin

--assign default output values

loadnum1 <= '0';

loadnum2 <= '0';

loadnum3 <= '0';

loadnum4 <= '0';

loadnum5 <= '0';

loadnum6 <= '0';

sample <= '0';

seldisplay <= 0;

numled <= "111111";

case lott_ps is

when res => --wait for 1st no

if next_no = '1' then

lott_ns <= s1;

else

lott_ns <= res;

end if;

when s1 => --take first sample

sample <= '1';

lott_ns <= s2;

when s2 => --save first no

loadnum1 <= '1';

numled <= "011111";

lott_ns <= s3;

when s3 => --wait for 2nd no

numled <= "011111";

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