MEMORY, MICROPROCESSOR, and ASIC phần 5 potx

Dynamic Random Access Memory 6-15

6.9.3 Charge-Coupling Sensing

Figure 6.18 shows the charge in bit-line levels due to coupling capacitor Cc. The MSB is sensed using

the reference level of half-Vcc, as mentioned earlier. The MSB generates the reference level for LSB

sensing. When Vs is defined as the absolute signal level of data “11” and “00”, the absolute signal level of

data “10” and “01” is one-third of Vs. Here, Vs is directly proportional to the ratio between storage

capacitor Cs and bit-line capacitance.

In the case of sensing data “11”, the initial signal level is Vs. After MSB sensing, the bit-line level in

Section B is changed for LSB sensing by the MSB through coupling capacitor Cc. The reference bit￾line in Section B is raised by Vc, and the other bit-line is reduced by Vc. For LSB sensing, Vc is one-third

of Vs due to the coupling capacitor Cc.

Using the two-step sensing scheme, the 2-bit data in a DRAM cell can be implemented.

References

1. Sekiguchi., T. et al., “An Experimental 220MHz 1Gb DRAM,” ISSCC Dig. Tech. Papers, pp. 252–253,

Feb. 1995.

2. Sugibayashi, T. et al., “A 1Gb DRAM for File Applications,” ISSCC Dig. Tech. Papers, pp. 254–255, Feb.

1995.

3. Murotani, T. et al., “A 4-Level Storage 4Gb DRAM,” ISSCC Dig. Tech. Papers, pp. 74–75, Feb. 1997.

4. Furuyama, T. et al., “An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic

Application,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 388–393, April 1989.

5. Ahlquist, C.N. et al., “A 16k 384-bit Dynamic RAM,” IEEE J. Solid-State Circuits, vol. SC-11, no. 3, Oct.

1976.

TABLE 6.2 Charge-Sharing Restore Scheme

FIGURE 6.18 Charge-coupling sensing.

6-16 Memory, Microprocessor, and ASIC

6. El-Mansy, Y. et al., “Design Parameters of the Hi-C SRAM cell,” IEEE J. Solid-State Circuits, vol. SC-17,

no. 5, Oct. 1982.

7. Lu, N.C. C., “Half-VDD Bit-Line Sensing Scheme in CMOS DRAM’s,” IEEE J. Solid-State Circuits, vol.

SC-19, no. 4, Aug. 1984.

8. Lu, N.C. C., “Advanced Cell Structures for Dynamic RAMs,” IEEE Circuits and Devices Magazine, pp.

27–36, Jan. 1989.

9. Mashiko, K. et al., “A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor

(FASIC) Cell,” IEEE J. Solid-State Circuits, vol. SC-22, no. 5, Oct. 1987.

10. Prince, B. et al., “Synchronous Dynamic RAM,” IEEE Spectrum, p. 44, Oct. 1992.

11. Yoo, J.-H. et al., “A 32-Bank 1Gb DRAM with 1GB/s Bandwidth,” ISSCC Dig. Tech. Papers, pp. 378–

379, Feb. 1996.

12. Nitta, Y. et al., “A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped

Memory Block and Distributed Bank Architecture,” ISSCC Dig. Tech. Papers, pp. 376–377, Feb.

1996.

13. Yoo, J.-H. et al., “A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 Gbyte/s Bandwidth,”

IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1635–1644, Nov. 1996.

14. Saeki, T. et al., “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror

Delay,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1656–1668, Nov. 1996.

15. Choi, Y. et al., “16Mb Synchronous DRAM with 125Mbyte/s Data Rate,” IEEE J. Solid-State Circuits,

vol. 29, no. 4, April 1994.

16. Sakashita, N. et al., “A 1.6GB/s Data-Rate 1-Gb Synchronous DRAM with Hierarchical Square

Memory Block and Distributed Bank Architecture,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp.

1645–1655, Nov. 1996.

17. Okuda, T. et al., “A Four-Level Storage 4-Gb DRAM,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp.

1743–1747, Nov. 1997.

18. Prince, B., Semiconductor Memories, 2nd edition, John Wiley & Sons, 1993.

19. Prince, B., High Performance Memories New Architecture DRAMs and SRAMs Evolution and Function, 1st

edition, Betty Prince, 1996.

20. Toshiba Applications Specific DRAM Databook, D-20, 1994.

7-1

7

Low-Power Memory

Circuits

7.1 Introduction 7-1

7.2 Read-Only Memory (ROM) 7-2

Sources of Power Dissipation

Low-Power ROMs

7.3 Flash Memory 7-4

Low-Power Circuit Techniques for Flash Memories

7.4 Ferroelectric Memory (FeRAM) 7-8

7.5 Static Random-Access Memory (SRAM) 7-14

Low-Power SRAMs

7.6 Dynamic Random-Access Memory (DRAM) 7-25

Low-Power DRAM Circuits

7.7 Conclusion 7-35

7.1 Introduction

In recent years, rapid development in VLSI fabrication has led to decreased device geometries and

increased transistor densities of integrated circuits, and circuits with high complexities and very high

frequencies have started to emerge. Such circuits consume an excessive amount of power and generate

an increased amount of heat. Circuits with excessive power dissipation are more susceptible to run￾time failures and present serious reliability problems. Increased temperature from high-power processors

tends to exacerbate several silicon failure mechanisms. Every 10°C increase in operating temperature

approximately doubles a component’s failure rate. Increasingly expensive packaging and cooling strategies

are required as chip power increases.1,2 Due to these concerns, circuit designers are realizing the

importance of limiting power consumption and improving energy efficiency at all levels of design. The

second driving force behind the low-power design phenomenon is a growing class of personal computing

devices, such as portable desktops, digital pens, audio-and video-based multimedia products, and

wireless communications and imaging systems, such as personal digital assistants, personal communicators,

and smart cards. These devices and systems demand high-speed, high-throughput computations, complex

functionalities, and often real-time processing capabilities.3,4 The performance of these devices is limited

by the size, weight, and lifetime of batteries. Serious reliability problems, increased design costs, and battery￾operated applications have prompted the IC design community to look more aggressively for new approaches and

methodologies that produce more power-efficient designs, which means significant reductions in power consumption for

the same level of performance.

Memory circuits form an integral part of every system design as dynamic RAMs, static RAMs,

ferroelectric RAMs, ROMs, or Flash memories significantly contribute to system-level power

consumption. Two examples of recently presented reduced-power processors show that 43% and

50.3%, respectively, of the total system power consumption is attributed to memory circuits.5,6 Therefore,

reducing the power dissipation in memories can significantly improve the system power-efficiency,

performance, reliability, and overall costs.

0-8493-1737-1/03/$0.00+$1.50

© 2003 by CRC Press LLC

Martin Margala

University of Alberta

7-2 Memory, Microprocessor, and ASIC

In this chapter, all sources of power consumption in different types of memories will be identified;

several low-power techniques will be presented; and the latest developments in low-power memories

will be analyzed.

7.2 Read-Only Memory (ROM)

ROMs are widely used in a variety of applications (permanent code storage for microprocessors or

data look-up tables in multimedia processors) for fixed long-term data storage. The high area density

and new submicron technologies with multiple metal layers increase the popularity of ROMs for a

low-voltage, low-power environment. In the following section, sources of power dissipation in ROMs

and applicable efficient low-power techniques are examined.

7.2.1 Sources of Power Dissipation

A basic block diagram of a ROM architecture is presented in Fig. 7.1.7,8 It consists of an address

decoder, a memory controller, a column multiplexer/driver, and a cell array. Table 7.1 lists an example of

a power dissipation in a 2 K×18 ROM designed in 0.6-µm CMOS technology at 3.3 V and clocked at

10 MHz.8

The cell array dissipates 89% of the total ROM power, and 11% is dissipated in the decoder,

control logic, and the drivers. The majority of the power consumed in the cell array is due to the

precharging of large capacitive bit-lines. During the read and write cycles, more than 18 bit-lines are

switched per access because the word-line selects more bit-lines than necessary. The example in Fig. 7.2

shows a 12–1 multiplexer and a bit-line with five transistors connected to it. This topology consumes

excessive amounts of power because 4 more bit-lines will switch instead of just one. The power

dissipated in the decoder, control logic, and drivers is due to the switching activity during the read and

precharge cycles and generating control signals for the entire memory

7.2.2 Low-Power ROMs

In order to significantly reduce the power consumption in ROMs, every part of the architecture has to

be targeted and multiple techniques have to be applied. De Angel and Swartzlander8 have identified

several architectural improvements in the cell array that minimize energy waste and improve efficiency.

These techniques include:

FIGURE 7.1 Basic ROM architecture. (© 1997, IEEE. With permission.)