MEMORY, MICROPROCESSOR, and ASIC phần 4 ppsx

Flash Memories 5-19

Solving Eqs. 5.22 and 5.24 with the assumption that only electrons at the Fermi level contribute to the

current yields the Fowler-Nordheim formula for the tunneling current density Jtunnel at high electric field:

(5.25)

This equation can also be expressed as

(5.26)

where a and ß are Fowler-Nordheim constants. The value of a is in the range of 4.7×10-5 to 6.32×10-

7

A/V2

and ß is in the range of 2.2×108

to 3.2×108

V/cm.47

The barrier height and tunneling distance determine the tunneling efficiency. Generally, the barrier

height at the Si-SiO2 interface is about 3.1 eV, which is material dependent. This parameter is determined

by the electron affinity and work function of the gate material. On the other hand, the tunneling

distance depends on the oxide thickness and the voltage drop across the oxide. As indicated in Eq. 5.26,

the tunneling current is exponentially proportional to the oxide field. Thus, a small variation in the

oxide thickness or voltage drop would lead to a significant tunneling current change. Figure 5.22

Shows the Fowler-Nordheim plot which can manifest the Fowler-Nordheim constants a and ß. The

Si-SiO2 barrier height can be determined based on this FN plot by quantum-mechanical (QM)

modeling.48

5.4.3 Comparisons of Electron Injection Operations

As mentioned in the above section, there are several operation schemes that can be employed for

electron injection, whereas only FN tunneling can be employed for ejecting electrons out of the

floating gate. Owing to the specific features of the electron injection mechanism, the utilization of an

electron injection scheme thereby determines the device structure design, process technology, and

circuit design. The main features of CHEI and FN tunneling for n-channel Flash memory cell and also

CHEI and BBHE injection for p-channel Flash memory cell are compared in Tables 5.1 and 5.2.

5.4.4 List of Operation Modes

The employment of different electron transport mechanisms to achieve the programming and erase

operations can lead to different device operation modes. Typically, in commercial applications, there are

FIGURE 5.22 Fowler-Nordheim plot of the thin oxide.

5-20 Memory, Microprocessor, and ASIC

three different operation modes for n-channel Flash cells and two different operation modes for p￾channel Flash cells. In the n-channel cell, as shown in Fig. 5.23, the write/erase operation modes

include: (1) programming operation with CHEI and erase operation with FN tunneling ejection at

source or drain side,6–8,49–61 as shown in Fig. 5.23(a), usually referred as NOR-type operation mode; (2)

programming operation with FN tunneling ejection at drain side and erase operation with FN tunnel￾ing injection through channel region,62–70 as shown in Fig. 5.23(b), usually referred as AND-type

operation mode; and (3) programming and erase operations with FN tunneling injection/ejection

through channel region,71–78 usually referred as NAND-type operation mode. As to the p-channel cell,

as shown in Fig. 5.24, the write/erase operation modes include: (1) programming operation with

CHEI at drain side and erase operation with FN tunneling ejection through channel region,9

as shown

in Fig. 5.24(a); and (2) programming operation with BBHE at drain side and erase operation with FN

tunneling injection through channel region,10,11 as shown in Fig. 5.24(b).

These operation modes not only lead to different device structures but also different memory array

architectures. The main purpose of utilizing various device structures for different operation modes is

based on the consideration of the operation efficiency, reliability requirements, and fabrication procedures.

In addition, the operation modes and device structures determine, and also are determined by, the

memory array architectures. In the following sections, the general improvements of the Flash device

structures and the array architectures for specific operation modes are described.

5.5 Variations of Device Structure

5.5.1 CHEI Enhancement

As mentioned above, alternative operation modes are proposed to achieve pervasive purposes and various

features, which are approached either by CHEI or FN tunneling injection. Furthermore, it is indicated

that over 90% of Flash memory product ever shipped are the CHEI-based Flash memory devices.79 With

the major manufacturers’ competition, many innovations and efforts are dedicated to improve the perfor￾mance and reliability of CHEI schemes.50,53,56,57,61,80–83 As described in Eq. 5.11, an increase in the electric

field can enhance the probability of the electrons gaining enough energy. Therefore, the major approach

to improve the channel hot electron injection efficiency is to enhance the electric field near the drain

TABLE 5.1 Comparisons of Fowler-Nordheim Tunneling and Channel Hot Electron

Injection as Programming Scheme for Stacked-Gate Devices

TABLE 5.2 Comparisons of Band-to-Band Tunneling Induced Hot Electron

Injection and Channel Hot Electron Injection as Programming Scheme for

Stacked-Gate Devices

Flash Memories 5-21

side. One of the structure modifications is utilizing the large-angle implanted p-pocket (LAP) around

the drain to improve the programming speed.56,57,60,83 LAP has also been used to enhance the punch￾through immunity for scaling down capability.50,53 As demonstrated in Fig. 5.13, the device with LAP

has a twofold maximum electric field of that in the device without LAP structure. According to our

previous report,83 additionally, the LAP cell with proper process design can satisfy the cell performance

requirements such as read current and punch-through resistance and also reliable long-term charge

retention. Besides, the utilization of the p-pocket implantation can achieve the low-voltage operation

and feasible scaling-down capability simultaneously.

5.5.2 FN Tunneling Enhancement

From the standpoint of power consumption, the programming/erase operation based on the FN tunneling

mechanism is unavoidable because of the low current during operation. As the dimension of Flash memory

continues scaling down, in order to lower the operation voltage, a thinner tunnel oxide is needed. However,

it is difficult to scale down the oxide thickness further due to reliability concerns. There are two ways to

overcome this issue. One method is to raise the tunneling efficiency by employing a layer of electron

injector on top of the tunnel oxide. Another method is to improve the gate coupling ratio of the memory

cell without changing the properties of the insulator between the floating gate and well.

FIGURE 5.23 Different n-channel Flash write/erase operations: (a) programmming operation with CHEI at

drain side and erase operation with FN tunneling ejection at source side; (b) programming operation with FN

tunneling ejection at drain side and erase operation with tunneling injection through channel region; and (c)

programming and erase operations with FN tunneling injection/ejection through channel region.