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Essentials of Electronic Testing
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ESSENTIALS OF ELECTRONIC TESTING
FOR DIGITAL, MEMORY AND
MIXED-SIGNAL VLSI CIRCUITS
FRONTIERS IN ELECTRONIC TESTING
Consulting Editor
Vishwani D. Agrawal
Books in the series:
Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4
Test Standard
A. Osseiran
ISBN: 0-7923-8686-8
Design for At-Speed Test, Diagnosis and Measurement
B. Nadeau-Dosti
ISBN: 0-79-8669-8
Delay Fault Testing for VLSI Circuits
A. K-T. Cheng
ISBN: 0-7923-8295-1
Research Perspectives and Case Studies in System Test and Diagnosis
J.W. Sheppard, W.R. Simpson
ISBN: 0-7923-8263-3
Formal Equivalence Checking and Design Debugging
S.-Y. Huang, K.-T. Cheng ISBN: 0-7923-8184-X
On-Line Testing for VLSI M. Nicolaidis, Y. Zorian
ISBN: 0-7923-8132-7
Defect Oriented Testing for CMOS Analog and Digital Circuits
M. Sachdev
ISBN: 0-7923-8083-5
Reasoning in Boolean Networks: Logic Synthesis and Verification
Using Testing Techniques
W. Kunz, D. Stoffel
ISBN: 0-7923-9921-8
Introduction to IDDQTesting S. Chakravarty, P.J. Thadikaran
ISBN: 0-7923-9945-5
Multi-Chip Module Test Strategies
Y. Zorian
ISBN: 0-7923-9920-X
Testing and Testable Design of High-Density Random-Access Memories
P. Mazumder, K. Chakraborty ISBN: 0-7923-9782-7
From Contamination to Defects, Faults and Yield Loss
J.B. Khare, W. Maly ISBN: 0-7923-9714-2
ESSENTIALS OF ELECTRONIC TESTING
FOR DIGITAL, MEMORY AND
MIXED-SIGNAL VLSI CIRCUITS
Michael L. Bushnell
Rutgers University
Vishwani D. Agrawal
Bell Labs, Lucent Technologies.
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
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3ULQW,6%1 792379918
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3ULQW by Lucent Technologies and Michael L. Bushnell.
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To Margaret Kalvar for her patient understanding, love, and support, which makes
my work possible — MLB.
To the women in my life, Premlata, Prathima, Victoria and Chitra,
and to my son, Vikas — VDA.
This page intentionally left blank
TABLE OF CONTENTS
PREFACE xv
ABOUT THE AUTHORS xvii
I INTRODUCTION TO TESTING 1
1 INTRODUCTION
1.1
1.2
1.3
1.4
1.5
Testing Philosophy ............................
Role of Testing ..............................
Digital and Analog VLSI Testing ....................
VLSI Technology Trends Affecting Testing ...............
Scope of this Book ............................
3
4
6
7
9
15
2 VLSI TESTING PROCESS AND TEST EQUIPMENT
2.1 How to Test Chips? ...........................
2.1.1 Types of Testing .........................
2.2 Automatic Test Equipment .......................
2.2.1
2.2.2
2.2.3
Advantest Model T6682 ATE ..................
LTX Fusion ATE ............................
Multi-Site Testing ........................
2.3
2.4
Electrical Parametric Testing ......................
Summary .................................
17
18
18
24
24
28
29
30
34
3 TEST ECONOMICS AND PRODUCT QUALITY
3.1 Test Economics ..............................
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Defining Costs ..........................
Production ............................
Benefit-Cost Analysis ......................
Economics of Testable Design ..................
The Rule of Ten ................... ........
3.2
3.3
Yield ....................................
Defect Level as a Quality Measure ...................
3.3.1
3.3.2
Test Data Analysis ........................
Defect Level Estimation .....................
35
36
36
38
41
42
44
44
47
48
50
viii TABLE OF CONTENTS
3.4 Summary ................................. 53
4 FAULT MODELING
4.1
4.2
4.3
4.4
4.5
Defects, Errors, and Faults .......................
Functional Versus Structural Testing ..................
Levels of Fault Models ..........................
A Glossary of Fault Models .......................
Single Stuck-at Fault ...........................
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
Fault Equivalence ........................
Equivalence of Single Stuck-at Faults ..............
Fault Collapsing .........................
Fault Dominance and Checkpoint Theorem ..........
Summary .............................
57
57
59
60
60
70
72
73
74
75
78
II TEST METHODS 81
5 LOGIC AND FAULT SIMULATION
5.1
5.2
5.3
Simulation for Design Verification ....................
Simulation for Test Evaluation .....................
Modeling Circuits for Simulation ....................
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Modeling Levels and Types of Simulators ...........
Hierarchical Connectivity Description .............
Gate-level Modeling of MOS Networks .............
Modeling Signal States ......................
Timing ..............................
5.4 Algorithms for True-Value Simulation .................
5.4.1
5.4.2
Compiled-Code Simulation ...................
Event-Driven Simulation .....................
5.5 Algorithms for Fault Simulation .....................
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Serial Fault Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Fault Simulation ....................
Deductive Fault Simulation ...................
Concurrent Fault Simulation ..................
Roth’s TEST-DETECT Algorithm ...............
Differential Fault Simulation ..................
5.6 Statistical Methods for Fault Simulation ................
5.6.1 Fault Sampling ..........................
5.7 Summary .................................
83
83
88
91
91
93
94
96
98
101
102
103
105
106
107
109
113
116
117
120
121
125
6 TESTABILITY MEASURES
6.1 SCOAP Controllability and Observability ...............
6.1.1
6.1.2
6.1.3
Combinational SCOAP Measures ................
Combinational Circuit Example .................
Sequential SCOAP Measures ..................
129
131
132
134
140
TABLE OF CONTENTS ix
6.1.4 Sequential Circuit Example ...................
6.2
6.3
High-Level Testability Measures .....................
Summary .................................
142
148
150
7 COMBINATIONAL CIRCUIT TEST GENERATION
7.1 Algorithms and Representations ....................
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
Structural vs. Functional Test .................
Definition of Automatic Test-Pattern Generator .......
Search Space Abstractions ....................
Algorithm Completeness .....................
ATPG Algebras .........................
Algorithm Types .........................
7.2
7.3
7.4
7.5
Redundancy Identification (RID) ....................
Testing as a Global Problem .......................
Definitions .................................
Significant Combinational ATPG Algorithms .............
7.5.1
7.5.2
7.5.3
7.5.4
D-Calculus and D-Algorithm (Roth) ..............
PODEM (Goel) ..........................
FAN (Fujiwara and Shimino) ..................
Advanced Algorithms ......................
7.6
7.7
7.8
Test Generation Systems .........................
Test Compaction .............................
Summary .................................
155
156
156
157
158
159
159
160
168
172
172
176
176
186
192
197
204
205
206
8 SEQUENTIAL CIRCUIT TEST GENERATION
8.1 ATPG for Single-Clock Synchronous Circuits .............
8.1.1 A Simplified Problem ......................
8.2 Time-Frame Expansion Method .....................
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Use of Nine-Valued Logic ....................
Development of Time-Frame Expansion Methods .......
Approximate Methods ......................
Implementation of Time-Frame Expansion Methods .....
Complexity of Sequential ATPG . ...............
Cycle-Free Circuits ........................
Cyclic Circuits ..........................
Clock Faults and Multiple-Clock Circuits ...........
Asynchronous Circuits ......................
8.3 Simulation-Based Sequential Circuit ATPG ..............
8.3.1
8.3.2
CONTEST Algorithm ......................
Genetic Algorithms ........................
8.4 Summary .................................
211
212
214
214
216
218
222
222
225
225
229
231
232
238
239
246
248
x TABLE OF CONTENTS
9 MEMORY TEST
9.1
9.2
9.3
Memory Density and Defect Trends ..................
Notation ..................................
Faults ...................................
9.3.1
9.3.2
Fault Manifestations .......................
Failure Mechanisms .......................
9.4
9.5
9.6
Memory Test Levels ...........................
March Test Notation ...........................
Fault Modeling ..............................
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
Diagnosis Versus Testing Needs .................
Reduced Functional Faults ...................
Relation Between Fault Models and Physical Defects .....
Multiple Fault Models ......................
Frequency of Faults .......................
9.7 Memory Testing .............................
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
Functional RAM Testing with March Tests . . ........
Testing RAM Neighborhood Pattern-Sensitive Faults .....
Testing RAM Technology and Layout-Related Faults .....
RAM Test Hierarchy .......................
Cache RAM Chip Testing ....................
Functional ROM Chip Testing .................
Electrical Parametric Testing ..................
9.8 Summary .................................
253
255
258
259
259
260
261
262
263
265
266
276
278
281
284
284
286
294
295
296
300
301
306
10 DSP-BASED ANALOG AND MIXED-SIGNAL TEST
10.1
10.2
10.3
Analog and Mixed-Signal Circuit Trends ................
Definitions .................................
Functional DSP-Based Testing .....................
10.3.1
10.3.2
10.3.3
10.3.4
Concept ..............................
Mechanism of DSP-Based Testers ................
Waveform Synthesis .......................
Waveform Sampling and Digitization ..............
10.4 Static ADC and DAC Testing Methods ................
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
Transmission vs. Intrinsic Parameters .............
Uncertainty and Distortion in Ideal ADCs ...........
DAC Transfer Function Error ..................
ADC Transfer Function Error ..................
Flash ADC Testing Methods ..................
DAC Testing Methods ......................
10.5 Realizing Emulated Instruments Using Fourier Transforms ......
10.5.1
10.5.2
10.5.3
10.5.4
Fourier Voltmeter ........................
Testing of Analog Devices Using Non-Coherent Sampling . .
Coherent Multi-Tone Testing ..................
ATE Vector Operations .....................
309
309
314
317
317
319
320
322
322
323
325
325
326
327
332
335
345
350
356
364
TABLE OF CONTENTS xi
10.6 CODEC Testing .............................
10.6.1
10.6.2
Considerations for CODEC Performance Tests ........
CODEC Tests ..........................
10.7
10.8
Dynamic Flash ADC Testing FFT Technique .............
Advanced Topics .............................
10.8.1
10.8.2
Event Digitization ........................
Measuring Random Noise ....................
10.9 Summary .................................
366
369
372
376
377
377
380
382
11 MODEL-BASED ANALOG AND MIXED-SIGNAL TEST
11.1
11.2
11.3
11.4
11.5
Analog Testing Difficulties ........................
Analog Fault Models ...........................
Levels of Abstraction ...........................
Types of Analog Testing . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Fault Simulation .........................
11.5.1
11.5.2
11.5.3
11.5.4
Motivation ............................
DC Fault Simulation of Nonlinear Circuits ...........
Linear Analog Circuit AC Fault Simulation ..........
Monte-Carlo Simulation .....................
11.6 Analog Automatic Test-Pattern Generation ..............
11.6.1
11.6.2
11.6.3
ATPG Using Sensitivities ....................
ATPG Using Signal Flow Graphs ................
Additional Methods .......................
11.7 Summary .................................
385
386
387
389
389
390
391
391
395
397
397
398
406
413
413
12 DELAY TEST
12.1
12.2
Delay Test Problem ...........................
Path-Delay Test .............................
12.2.1
12.2.2
Test Generation for Combinational Circuits ..........
Number of Paths in a Circuit ..................
12.3
12.4
Transition Faults .............................
Delay Test Methodologies ........................
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
Slow-Clock Combinational Test .................
Enhanced-Scan Test .......................
Normal-Scan Sequential Test ..................
Variable-Clock Non-Scan Sequential Test ...........
Rated-Clock Non-Scan Sequential Test .............
12.5 Practical Considerations in Delay Testing ...............
12.5.1 At-Speed Testing .........................
12.6 Summary .................................
417
417
420
424
427
428
429
429
430
431
432
434
434
435
436
13 IDDQ TEST
13.1
13.2
13.3
Motivation ................................
Faults Detected by Tests .....................
Testing Methods ..........................
439
439
441
446
xii TABLE OF CONTENTS
13.3.1
13.3.2
13.3.3
13.3.4
Fault Coverage Metrics ..................
Test Vector Selection from Stuck-Fault Vector Sets . .
Instrumentation Problems ....................
Current Limit Setting ......................
13.4
13.5
13.6
13.7
13.8
13.9
Surveys of Testing Effectiveness .................
Limitations of Testing .......................
Delta Testing ...........................
Built-In Current Testing .....................
Design for Testability .......................
Summary .................................
446
448
451
452
453
455
456
458
460
460
III DESIGN FOR TESTABILITY 463
14 DIGITAL DFT AND SCAN DESIGN
14.1
14.2
Ad-Hoc DFT Methods ..........................
Scan Design ................................
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
Scan Design Rules ........................
Tests for Scan Circuits ......................
Multiple Scan Registers .....................
Overheads of Scan Design ....................
Design Automation ..........................
Physical Design and Timing Verification of Scan .......
14.3
14.4
14.5
Partial-Scan Design ...........................
Variations of Scan ............................
Summary .................................
465
466
467
469
471
474
474
477
479
479
483
485
15 BUILT-IN SELF-TEST
15.1 The Economic Case for BIST ......................
15.1.1
15.1.2
Chip/Board Area Cost vs. Tester Cost .............
Chip/Board Area Cost vs. System Downtime Cost ......
15.2 Random Logic BIST ...........................
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
15.2.6
15.2.7
15.2.8
15.2.9
Definitions ............................
BIST Process ...........................
BIST Pattern Generation ....................
BIST Response Compaction ...................
Built-in Logic Block Observers .................
Test-Per-Clock BIST Systems ..................
Test-Per-Scan BIST Systems ..................
Circular Self-Test Path System .................
Circuit Initialization .......................
15.2.10
15.2.11
Device Level BIST ........................
Test Point Insertion .......................
15.3 Memory BIST .................................
15.3.1 Definitions ............................
489
490
492
494
495
495
496
498
512
519
521
521
525
526
526
528
529
530
TABLE OF CONTENTS xiii
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
March Test SRAM BIST ....................
SRAM BIST with MISR .....................
Neighborhood Pattern Sensitive Fault Test DRAM BIST . .
Transparent Memory BIST Tests ................
Complex Examples . . . .....................
15.4
15.5
Delay Fault BIST .............................
Summary .................................
532
534
536
539
539
540
543
16 BOUNDARY SCAN STANDARD
16.1 Motivation ................................
16.1.1 Purpose of Standard .......................
16.2 System Configuration with Boundary Scan ..............
16.2.1
16.2.2
16.2.3
TAP Controller and Port ....................
Boundary Scan Test Instructions ................
Pin Constraints of the Standard ................
16.3 Boundary Scan Description Language .................
16.3.1
16.3.2
BSDL Description Components .................
Pin Descriptions .........................
16.4 Summary .................................
549
550
552
553
553
557
564
569
570
571
572
17 ANALOG TEST BUS STANDARD
17.1
17.2
Analog Circuit Design for Testability ..................
Analog Test Bus (ATB) .........................
17.2.1
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
Targeted Analog Faults .....................
Analog Test Access Port (ATAP) ................
Test Bus Interface Circuit (TBIC) ...............
Analog Boundary Module (ABM) ...............
Instructions for 1149.4 Standard ................
Other 1149.4 Standard Features ................
17.3 Summary .................................
575
576
576
577
579
580
583
585
589
591
18 SYSTEM TEST AND CORE-BASED DESIGN
18.1
18.2
System Test Problem Defined ......................
Functional Test ..............................
18.2.1 Microprocessor Test .......................
18.3 Diagnostic Test ..............................
18.3.1
18.3.2
18.3.3
Fault Dictionary .........................
Diagnostic Tree ..........................
A System Test Example .....................
18.4
18.5
18.6
18.7
18.8
Testable System Design .........................
Core-Based Design and Test-Wrapper .................
A Test Architecture for System-on-a-Chip (SOC) ...........
An Integrated Design and Test Approach ...............
Summary .................................
595
596
597
598
598
599
600
602
604
606
607
608
610
xiv TABLE OF CONTENTS
19 THE FUTURE OF TESTING 613
A CYCLIC REDUNDANCY CODE THEORY
A.1
A.2
Polynomial Multiplier ..........................
Polynomial Divider ............................
615
616
617
B PRIMITIVE POLYNOMIALS OF DEGREE 1 TO 100 619
C BOOKS ON TESTING
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
General and Tutorial ...........................
Analog and Mixed-Signal Circuit Test .................
ATE, Test Programming, and Production Test ............
Board and MCM Test and Boundary Scan ...............
Built-In Self-Test .............................
Delay Fault Test .............................
Design for Testability ..........................
Fault Modeling ..............................
Fault Tolerance and Diagnosis ......................
C.10
C.11
C.12
C.13
C.14
C.15
C.16
C.17
C.18
C.19
C.20
C.21
C.22
Formal Verification ............................
High-Level Test and Verification ....................
Test .................................
Memory Test ...............................
Microprocessor Verification and Test ..................
Semiconductor Defect Mechanisms ...................
System Test ................................
Test Economics ..............................
Test Evaluation ..............................
Test Generation ..............................
Periodicals .................................
Conferences and Workshops .......................
Web Sites .................................
621
621
622
622
623
624
624
624
625
625
625
626
626
626
627
627
627
627
628
628
628
629
629
BIBLIOGRAPHY 631
INDEX 671