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Status Register

The Status Register is a 16-bit register that provides the device status.

The bits are defined in the status register as follows:

Bit Function

0:4 Reserved

5 66 MHz Capable

6 UDF Supported

7 Fast Back-to-Back Capable

8 Data Parity Reported

9:10 Device Select

11 Signaled Target Abort

12 Received Target Abort

13 Received Master Abort

14 Signaled System Error

15 Detected Parity Error

Revision ID

The revision ID register contains an 8-bit value assigned by the manufac￾turer that contains the device revision number.

Class Code

The class code register is a 24-bit register that defines the base class, sub￾class and programming interface.

0:7 8:15 16:23

Programming interface Sub-Class Code Class Code

The class code, sub-class code and programming interface are defined by

the PCI Interface specification.

Cache Line Size

The cache line size register is an 8-bit register that defines the system cache

line size in double word increments.

213 Appendix B

PCI

Latency Timer

The latency time is an 8-bit register that defines the minimum amount of

time, in PCI clock cycles, that the bus master can retain ownership of the bus.

Header Type

The header type register is an 8-bit register that defines the type of device.

Bit 7 is set to 0 or 1, defining single function or multi function.

BIST

The BIST register is an 8-bit register that can be used for PCI devices that

implement Built In Self Test (BIST).

Base Address Registers

The base address registers are 32-bit registers used to determine the PCI

memory mapped and IO spaces used by the device. A PCI device may have

up to 6 base address registers that are used to utilize memory mapped or IO

address space.

CardBus CIS Pointer

The CardBus CIS Pointer Register is a 32-bit register implemented by

devices that share silicon between the cardbus and PCI bus.

Subsystem Vendor ID

The subsystem vendor ID is a 16-bit register used to uniquely identify an

add-in card. The subsystem vendor ID is obtained from the PCI-SIG.

Subsystem ID

The subsystem ID is a 16-bit register used to define additional features for a

PCI device. The subsystem ID is defined by the vendor.

Expansion ROM Address

For devices that that contain power-on self test (POST) code, BIOS and

interrupt service routines, the Expansion ROM address register is a 32-bit

register that contains the starting address and size of the ROM code.