Design and Implementation of VLSI Systems_Lecture 06: Circuit characterization and performance

Design and Implementation

of VLSI Systems

Lecture 06

Thuan Nguyen

Faculty of Electronics and Telecommunications,

University of Science, VNU HCMUS

Spring 2011

1

INTRODUCTION

 The delay of a logic gate:

C: load capacitance

t ∝

��

��

∆�� I: output current

∆��: output voltage swing

2

 nMOS provides more current than pMOS for the same size

and capacitance

 Static CMOS requires both nMOS and pMOS on each

input.

 All the node voltages in static CMOS must transition

between 0 and VDD  propagation delay + power

consumption.

 Circuit families

LECTURE 06: CIRCUIT CHARACTERIZATION &

PERFORMANCE ESTIMATION

1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

3

LECTURE 06: CIRCUIT CHARACTERIZATION &

PERFORMANCE ESTIMATION

1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

4

OUTLINE

 Bubble Pushing

 Compound Gates

 Logical Effort Example

 Input Ordering

 Asymmetric Gates

 Skewed Gates

 Best P/N ratio

5

EXAMPLE 1

module mux(input s, d0, d1,

output y);

assign y = s ? d1 : d0;

endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0

S

D1

S

Y

6

EXAMPLE 2

Y

D0

S

D1

S

7

module mux(input s, d0, d1,

output y);

assign y = s ? d1 : d0;

endmodule

2) Sketch a design using NAND, NOR, and NOT

gates. Assume ~S is available.