An Experimental Approach to CDMA and Interference Mitigation phần 9 potx

5. Interference Mitigation Processor ASIC’s Design 217

up possible asynchronous transitions. The pad cell used by all output pins is

the B2TR_TC, a 3.3V output pad with slew-rate control and a maximum DC

current of 2 mA, suited for loads up to 50 pF.

PAD

placement

PAD

placement

ICpack

Veriloggate level netlist PAD list Veriloggate level netlist Blast Fusi on

Place and route phases:

• f loor planningand

macro placement

• power routing

• cell placement and

global routing

• clock tree sy nthesis

• f iller cells

• f inal routing

• parameters extraction

Verilog

post-layout

netlist

Parasitic

parameters GDSII

layout

GDSII

layout

Formal

v erif ication

Formal

v erif ication

Formality

Static

Timing

Analy sis

Static

Timing

Analy sis

PrimeTime

Post-lay out

simulation

Post-lay out

simulation

VSS

Layout

finishing

Layout

finishing

OPUS

GDSII

final layout

GDSII

final layout

DRC

LVS

DRC

LVS

Calibre

Tapeout Magma

Synopsys

Mentor

Cadence

PAD

placement

PAD

placement

ICpack

Veriloggate level netlist PAD list Veriloggate level netlist Blast Fusi on

Place and route phases:

• f loor planningand

macro placement

• power routing

• cell placement and

global routing

• clock tree sy nthesis

• f iller cells

• f inal routing

• parameters extraction

Verilog

post-layout

netlist

Parasitic

parameters GDSII

layout

GDSII

layout

Formal

v erif ication

Formal

v erif ication

Formality

Static

Timing

Analy sis

Static

Timing

Analy sis

PrimeTime

Post-lay out

simulation

Post-lay out

simulation

VSS

Layout

finishing

Layout

finishing

OPUS

GDSII

final layout

GDSII

final layout

DRC

LVS

DRC

LVS

Calibre

Tapeout Magma

Synopsys

Mentor

Cadence

Figure 5-26. Back End design flow.

Identification of the correct number of power supply pads calls for power

consumption estimation. This was accomplished following proper guidelines

provided by the silicon foundry. A first instance, rough power estimate was

quickly calculated by Synopsys Design Compiler, which can combine the

registers switching activity monitored during an RTL simulation with statis￾tically estimated activities for the remaining combinatorial cells. This

218 Chapter 5

method resulted in an estimate of about 12 mW for the core power consump￾tion, at a clock speed of 32.768 MHz, and with a chip rate of 4.096 Mchip/s.

IOLIB_80 : 220 + 80 × 11 + 220 = 1320 µm IOLIB_50 : 380 + 725 + 380 = 1485 µm

Figure 5-27. Die area with different pad libraries.

According to the above mentioned guidelines, 2 VDD3IOCO pads were

inserted in order to provide the 3.3 V power supply to all I/O pads, whilst 2

VDDIOCO pads were included to provide the 1.8 V power supply for the

core and the internal I/O cells buffers. Moreover, 5 VSSIOCO ground pads

were put in the remaining places. All I/O and supply pads include Electro￾Static Discharge (ESD) protections, ruling out the need for specific cells.

Pad cells were added to the netlist after the logic synthesis, while their

placement was performed as the first Back End step by means of the ICpack

tool. This software placed the pad cells taking the desired order into account

(as in Figure 5-1), and checking all the packaging rules. Its output was a

Physical Design Exchange Format (PDEF) file, which is a proprietary file

format used by Synopsys to describe placement information and clustering

of logic cells. Supplementary spaces were added between the most periph￾eral pads and the corner cells in order to avoid bonding rules violations. This

resulted in a final die area of 1528×1528 µm2

with the IOLIB_80 pads. Start￾ing from Figure 5-27, and considering this added length and the amount of

space necessary for RAM buses routing, the 80 µm pad library still revealed

the correct choice.

In order to avoid the simultaneous switching of all the output pads, which

could impair power supply levels, additional delay cells were inserted be￾tween final registers and Outr/Outi output pads to provide a set of differ￾ent delays (however negligible with respect to the output signals symbol

rate).