Test and Diagnosis of Analogue, Mixed-Signal and RF Integrated Circuits: The System on Chip Approach

Test and Diagnosis of

Analogue, Mixed-signal and

RF Integrated Circuits

The system on chip approach

Edited by Yichuang Sun

The Institution of Engineering and Technology

Published by The Institution of Engineering and Technology, London, United Kingdom

© 2008 The Institution of Engineering and Technology

First published 2008

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British Library Cataloguing in Publication Data

Test and diagnosis of analogue, mixed-signal and RF

integrated circuits : the system on chip approach. –

(Circuits, devices & systems ; v. 19)

1. Linear integrated circuits – Testing 2. Mixed signal

circuits – Testing 3. Radio frequency integrated circuits – Testing

I. Sun, Yichuang II. Institution of Engineering and Technology

621.3’815’0287

ISBN 978-0-86341-745-0

Typeset in India by Newgen Imaging Systems (P) Ltd, Chennai

Printed in the UK by Athenaeum Press Ltd, Gateshead, Tyne & Wear

Preface

System on chip (SoC) integrated circuits (ICs) for communications, multimedia and

computer applications are receiving considerable international attention. One exam￾ple of a SoC is a single-chip transceiver. Modern microelectronic design processes

adopt a mixed-signal approach since a SoC is a mixed-signal system that includes

both analogue and digital circuits. There are several IC technologies currently avail￾able, however, the low-cost and readily available CMOS technique is the mainstream

technology used in IC production for applications such as computer hard disk drive

systems, sensors and sensing systems for health care, video, image and display sys￾tems and cable modems for wired communications, radio frequency (RF) transceivers

for wireless communications and high-speed transceivers for optical communications.

Currently, microelectronic circuits and systems are mainly based on submicron and

deep-submicron CMOS technologies, although nano-CMOS technology has already

been used in computer, communication and multimedia chip design. While still push￾ing the limits of CMOS, preparation for the post-CMOS era is well under way with

many other potential alternatives being actively pursued.

There is an increasing interest in the testing of SoC devices as automatic testing

becomes crucially important to drive down the overall cost of SoC devices due to the

imperfect nature of the manufacturing process and its associated tolerances. Tradi￾tional external test has become more and more irrelevant for SoC devices, because

these devices have a very limited number of test nodes. Design for testability (DfT)

and built-in self-test (BIST) approaches have thus been the choice for many applica￾tions. The concept of on chip test systems including test generation, measurement and

processing has also been proposed for complex integrated systems. Test and fault diag￾nosis of analogue and mixed-signal circuits, however, is much more difficult than that

of digital circuits due to tolerances, parasitics and non-linearities, and thus it remains

a bottleneck for automatic SoC test. Recently, the closely related tuning, calibration

and correction issues of analogue, mixed-signal and RF circuits have been intensively

studied. However, the papers on testing, diagnosis and tuning have been published

in a diverse range of journals and conferences, and thus they have been treated quite

separately by the associated communities. For example, work on tuning has been

mainly published in journals and conferences concerned with circuit design and has

not therefore come to the attention of the testing community. Similarly, analogue fault

xvi Test and diagnosis of analogue, mixed-signal and RF integrated circuits

diagnosis was mainly investigated by circuit theorists in the past, although it has now

become a serious topic in the testing community.

The scope of this book is to consider the whole range of automatic testing, diagno￾sis and tuning of analogue, mixed-signal and RF ICs and systems. It aims to provide

a comprehensive treatment of testing, diagnosis and tuning in a coherent way and

to report systematically the most recent developments in all these areas in a single

source for the first time. The book attempts to provide a balanced view of the three

important topics, however, stress has been put on the testing side. Motivated by recent

SoC test concepts, the diagnosis, testing and tuning issues of analogue, mixed-signal

and RF circuits are addressed, in particular, from the SoC perspective, which forms

another unique feature of this book.

The book contains 11 chapters written by leading international researchers in

the subject areas. It covers three theme topics: diagnosis, testing and tuning. The

first four chapters are concerned with fault diagnosis of analogue circuits. Chapter

1 systematically presents various circuit-theory-based diagnosis methodologies for

both linear and non-linear circuits including some material not previously available

in the public domain. This chapter also serves as an overview of fault diagnosis.

The following three chapters cover the three most popular diagnosis approaches;

the symbolic function, neural network and hierarchical decomposition techniques,

respectively. Then testing of analogue, mixed-signal and RF ICs is discussed exten￾sively in Chapters 5-10. Chapter 5 gives a general review of all aspects of testing with

emphasis on DfT and BIST. Chapters 6–10 focus in depth on recent advances in test￾ing analogue filters, data converters, sigma-delta modulators, phase-locked loops, RF

transceivers and components, respectively. Finally, Chapter 11 discusses auto-tuning

and calibration of analogue, mixed-signal and RF circuits including continuous-time

filters, voltage-controlled oscillators and phase-locked loops synthesizers, impedance

matching networks and antenna tuning units.

The book can be used as a text or reference for a broad range of readers from

both academia and industry. It is especially useful for those who wish to gain a

viewpoint from which to understand the relationship of diagnosis, testing and tuning.

An indispensible reference companion to researchers and engineers in electronic and

electrical engineering, the book is also intended to be a text for graduate and senior

undergraduate students, as may be appropriate.

I would like to thank staff members in the Publishing Department of the IET

for their support and assistance, especially the former Commissioning Editors Sarah

Kramer and Nick Canty and the current Commissioning Editor, Lisa Reading. I am

very grateful to the chapter authors for their considerable efforts in contributing these

high-quality chapters; their professionalism is highly appreciated. I must also thank

my wife Xiaohui, son Bo and daughter Lucy for their understanding and support;

without them behind me this book would not have been possible.

As a final note, it has been my long dream to write or edit something in the topic

area of this book. The first research paper published in my academic career was about

fault diagnosis in analogue circuits. This was over 20 years ago when I studied for

the MSc degree. The real motivation for doing this book, however, came along with

the proposal for a special issue on analogue and mixed-signal test for SoCs for IEE

Preface xvii

Proceedings: Circuits, Devices and Systems (published in 2004). It has since been

a long journey for the book to come into being as you see now, however, the book

has indeed been significantly improved with the time during the editorial process.

I sincerely hope that the efforts from the editor and authors pay off as a truly useful

and long-lasting companion in your successful career.

Yichuang Sun

Contents

Preface xv

List of contributors xix

1 Fault diagnosis of linear and non-linear analogue circuits 1

Yichuang Sun

1.1 Introduction 1

1.2 Multiple-fault diagnosis of linear circuits 3

1.2.1 Fault incremental circuit 3

1.2.2 Branch-fault diagnosis 4

1.2.3 Testability analysis and design for testability 6

1.2.4 Bilinear function and multiple excitation method 8

1.2.5 Node-fault diagnosis 9

1.2.6 Parameter identification after k-node fault location 10

1.2.7 Cutset-fault diagnosis 12

1.2.8 Tolerance effects and treatment 15

1.3 Class-fault diagnosis of analogue circuits 15

1.3.1 Class-fault diagnosis and general algebraic method for

classification 16

1.3.2 Class-fault diagnosis and topological technique for

classification 18

1.3.3 t-class-fault diagnosis and topological method for

classification 19

1.4 Fault diagnosis of non-linear circuits 21

1.4.1 Fault modelling and fault incremental circuits 21

1.4.2 Fault location and identification 24

1.4.3 Alternative fault incremental circuits and fault

diagnosis 26

1.5 Recent advances in fault diagnosis of analogue circuits 29

1.5.1 Test node selection and test signal generation 29

viii Test and diagnosis of analogue, mixed-signal and RF integrated circuits

1.5.2 Symbolic approach for fault diagnosis of analogue

circuits 30

1.5.3 Neural-network- and wavelet-based methods for

analogue fault diagnosis 31

1.5.4 Hierarchical approach for large-scale circuit fault

diagnosis 31

1.6 Summary 32

1.7 References 33

2 Symbolic function approaches for analogue fault diagnosis 37

Stefano Manetti and Maria Cristina Piccirilli

2.1 Introduction 37

2.2 Symbolic analysis 39

2.2.1 Symbolic analysis techniques 40

2.2.2 The SAPWIN program 40

2.3 Testability and ambiguity groups 41

2.3.1 Algorithms for testability evaluation 42

2.3.2 Ambiguity groups 47

2.3.3 Singular-value decomposition approach 52

2.3.4 Testability analysis of non-linear circuits 57

2.4 Fault diagnosis of linear analogue circuits 57

2.4.1 Techniques based on bilinear decomposition of fault

equations 59

2.4.2 Newton–Raphson-based approach 62

2.4.3 Selection of the test frequencies 67

2.5 Fault diagnosis of non-linear circuits 71

2.5.1 PWL models 72

2.5.2 Transient analysis models for reactive components 73

2.5.3 The Katznelson-type algorithm 73

2.5.4 Circuit fault diagnosis application 74

2.5.5 The SAPDEC program 75

2.6 Conclusions 77

2.7 References 77

3 Neural-network-based approaches for analogue circuit fault

diagnosis 83

Yichuang Sun and Yigang He

3.1 Introduction 83

3.2 Fault diagnosis of analogue circuits with tolerances using

artificial neural networks 84

3.2.1 Artificial neural networks 85

3.2.2 Fault diagnosis of analogue circuits 87

3.2.3 Fault diagnosis using ANNs 88

List of contents ix

3.2.4 Neural-network approach for fault diagnosis of

large-scale analogue circuits 90

3.2.5 Illustrative examples 90

3.3 Wavelet-based neural-network technique for fault diagnosis of

analogue circuits with noise 94

3.3.1 Wavelet decomposition 94

3.3.2 Wavelet feature extraction of noisy signals 95

3.3.3 WNNs 96

3.3.4 WNN algorithm for fault diagnosis 97

3.3.5 Example circuits and results 98

3.4 Neural-network-based L1-norm optimization approach for fault

diagnosis of non-linear circuits 100

3.4.1 L1-norm optimization approach for fault location of

non-linear circuits 103

3.4.2 NNs applied to L1-norm fault diagnosis of non-linear

circuits 105

3.4.3 Illustrative example 109

3.5 Summary 110

3.6 References 111

4 Hierarchical/decomposition techniques for large-scale analogue

diagnosis 113

Peter Shepherd

4.1 Introduction 113

4.1.1 Diagnosis definitions 114

4.2 Background to analogue fault diagnosis 115

4.2.1 Simulation before test 115

4.2.2 Simulation after test 116

4.3 Hierarchical techniques 121

4.3.1 Simulation after test 121

4.3.2 Simulation before test 131

4.3.3 Mixed SBT/SAT approaches 135

4.4 Conclusions 137

4.5 References 138

5 DFT and BIST techniques for analogue and mixed-signal test 141

Mona Safi-Harb and Gordon Roberts

5.1 Introduction 141

5.2 Background 142

5.3 Signal generation 146

5.3.1 Direct digital frequency synthesis 146

5.3.2 Oscillator-based approaches 147

5.3.3 Memory-based signal generation 148

x Test and diagnosis of analogue, mixed-signal and RF integrated circuits

5.3.4 Multi-tones 149

5.3.5 Area overhead 150

5.4 Signal capture 151

5.5 Timing measurements and jitter analysers 154

5.5.1 Single counter 154

5.5.2 Analogue-based interpolation techniques:

time-to-voltage converter 155

5.5.3 Digital phase-initerpolation techniques: delay line 156

5.5.4 Vernier delay line 157

5.5.5 Component-invariant VDL for jitter

measurement 159

5.5.6 Analogue-based jitter measurement device 160

5.5.7 Time amplification 162

5.5.8 PLL and DLL – injection methods for PLL tests 163

5.6 Calibration techniques for TMU and TDC 164

5.7 Complete on-chip test core: proposed architecture in

Reference 11 and its versatile applications 166

5.7.1 Attractive and flexible architecture 166

5.7.2 Oscilloscope/curve tracing 168

5.7.3 Coherent sampling 169

5.7.4 Time domain reflectometry/transmission 169

5.7.5 Crosstalk 169

5.7.6 Supply/substrate noise 170

5.7.7 RF testing – amplifier resonance 171

5.7.8 Limitations of the proposed architecture in

Reference 11 172

5.8 Recent trends 172

5.9 Conclusions 173

5.10 References 174

6 Design-for-testability of analogue filters 179

Yichuang Sun and Masood-ul Hasan

6.1 Introduction 179

6.2 DfT by bypassing 181

6.2.1 Bypassing by bandwidth broadening 181

6.2.2 Bypassing using duplicated/switched opamp 186

6.3 DfT by multiplexing 188

6.3.1 Tow-Thomas biquad filter 188

6.3.2 The Kerwin–Huelsman–Newcomb biquad filter 189

6.3.3 Second-order OTA-C filter 190

6.4 OBT of analogue filters 192

6.4.1 Test transformations of active-RC filters 193

6.4.2 OBT of OTA-C filters 196

6.4.3 OBT of SC biquadratic filter 199

List of contents xi

6.5 Testing of high-order analogue filters 201

6.5.1 Testing of high-order filters using bypassing 202

6.5.2 Testing of high-order cascade filters using

multiplexing 203

6.5.3 Test of MLF OTA-C filters using multiplexing 205

6.5.4 OBT structures for high-order OTA-C filters 207

6.6 Summary 210

6.7 References 210

7 Test of A/D converters: From converter characteristics to built-in

self-test proposals 213

Andreas Lechner and Andrew Richardson

7.1 Introduction 213

7.2 A/D conversion 214

7.2.1 Static A/D converter performance parameters 216

7.2.2 Dynamic A/D converter performance parameters 218

7.3 A/D converter test approaches 220

7.3.1 Set-up for A/D converter test 220

7.3.2 Capturing the test response 221

7.3.3 Static performance parameter test 222

7.3.4 Dynamic performance parameter test 226

7.4 A/D converter built-in self-test 228

7.5 Summary and conclusions 231

7.6 References 232

8 Test of
converters 235

Gildas Leger and Adoración Rueda

8.1 Introduction 235

8.2 An overview of
modulation: opening the ADC black box 236

8.2.1 Principle of operation:
modulation and noise

shaping 236

8.2.2 Digital filtering and decimation 238

8.2.3
modulator architecture 239

8.3 Characterization of
converters 243

8.3.1 Consequences of
modulation for ADC

characterization 243

8.3.2 Static performance 244

8.3.3 Dynamic performance 246

8.3.4 Applying a FFT with success 248

8.4 Test of
converters 254

8.4.1 Limitations of the functional approach 255

8.4.2 The built-in self-test approach 255

8.5 Model-based testing 259

8.5.1 Model-based test concepts 259

xii Test and diagnosis of analogue, mixed-signal and RF integrated circuits

8.5.2 Polynomial model-based BIST 262

8.5.3 Behavioural model-based BIST 264

8.6 Conclusions 271

8.7 References 273

9 Phase-locked loop test methodologies: Current characterization

and production test practices 277

Martin John Burbidge and Andrew Richardson

9.1 Introduction: Phase-locked loop operation and test

motivations 277

9.1.1 PLL key elements’ operation and test issues 277

9.1.2 Typical CP-PLL test specifications 282

9.2 Traditional test techniques 287

9.2.1 Characterization focused tests 287

9.2.2 Production test focused 298

9.3 BIST techniques 301

9.4 Summary and conclusions 306

9.5 References 306

10 On-chip testing techniques for RF wireless transceiver systems

and components 309

Alberto Valdes-Garcia, Jose Silva-Martinez,

Edgar Sanchez-Sinencio

10.1 Introduction 309

10.2 Frequency-response test system for analogue baseband

circuits 311

10.2.1 Principle of operation 311

10.2.2 Testing methodology 313

10.2.3 Implementation as a complete on-chip test system

with a digital interface 314

10.2.4 Experimental evaluation of the FRCS 319

10.3 CMOS amplitude detector for on-chip testing of

RF circuits 324

10.3.1 Gain and 1-dB compression point measurement

with amplitude detectors 327

10.3.2 CMOS RF amplitude detector design 328

10.3.3 Experimental results 330

10.4 Architecture for on-chip testing of wireless transceivers 333

10.4.1 Switched loop-back architecture 333

10.4.2 Overall testing strategy 337

10.4.3 Simulation results 339

10.5 Summary and outlook 342

10.6 References 343

List of contents xiii

11 Tuning and calibration of analogue, mixed-signal and RF circuits 347

James Moritz and Yichuang Sun

11.1 Introduction 347

11.2 On-chip filter tuning 348

11.2.1 Tuning system requirements for on-chip filters 348

11.2.2 Frequency tuning and Q tuning 349

11.2.3 Online and offline tuning 352

11.2.4 Master–slave tuning 354

11.2.5 Frequency tuning methods 355

11.2.6 Q tuning techniques 359

11.2.7 Tuning of high-order leapfrog filters 360

11.3 Self-calibration techniques for PLL frequency synthesizers 365

11.3.1 Need for calibration in PLL synthesizers 365

11.3.2 PLL synthesizer with calibrated VCO 366

11.3.3 Automatic PLL calibration 368

11.3.4 Other PLL synthesizer calibration applications 370

11.4 On-chip antenna impedance matching 371

11.4.1 Requirement for on-chip antenna impedance

matching 371

11.4.2 Matching network 373

11.4.3 Impedance sensors 376

11.4.4 Tuning algorithms 377

11.5 Conclusions 378

11.6 References 378

Index 383

Chapter 1

Fault diagnosis of linear and non-linear

analogue circuits

Yichuang Sun

1.1 Introduction

Fault diagnosis of analogue circuits is becoming ever-increasingly important owing

to the rapidly increasing complexity of integrated circuits (ICs) and systems [1–62].

Recent interest in mixed-signal systems on a chip provides further motivation for

analogue fault diagnosis automation. Fault diagnosis of analogue circuits started with

an investigation of the solvability of network component values in 1960 [13] and has

been an active research area ever since. Methods for analogue fault diagnosis can

be broadly divided into simulation before test (SBT) or simulation-after-test (SAT)

techniques depending on whether simulation is mainly conducted before test or after

test. The most representative SBT technique is the fault dictionary approach, while

SAT techniques include the parameter identification and fault verification approaches.

The types of fault most widely considered from the viewpoints of fault diagnosis

and location are soft faults and hard faults. The former are caused by deviations in

component values from their nominal ones, whereas the latter refer to catastrophic

changes such as open circuits and short circuits.

The fault dictionary method is concerned with the construction of a fault dictio￾nary by simulating the effects of a set of typical faults and recording the pattern of

the observable outputs [11, 12]. To construct a fault dictionary, all potential faults are

listed and the stimuli are selected. The circuit under test (CUT) is then simulated for

the fault-free case and all faulty cases. The signatures of the responses are stored and

organized in the dictionary. Ambiguity sets are put together as a single entry. After

test, the measured signatures are compared with those stored in the dictionary for

the fittest to decide the faults. The fault dictionary method has the smallest after-test

computation levels mainly resulting from the comparison of measured test data with

those already stored in the dictionary to decide the faults. Because of this, the fault

2 Test and diagnosis of analogue, mixed-signal and RF integrated circuits

dictionary method is used practically in the fault diagnosis of analogue and mixed￾signal circuits, especially for single hard-fault diagnosis. The drawback of the method

is the large number of SBT computations that are needed for the construction of a

fault dictionary, especially for multiple-fault and soft-fault diagnosis of a large cir￾cuit. Methods for effective fault simulation and large-change sensitivity computation

are thus needed [6–10]. Tolerance effects need to be considered as simulations are

conducted at nominal values for fault-free components.

The parameter identification approach calculates all actual component values from

a set of linear or non-linear equations after test and compares them with their nominal

values to decide which components are faulty [13–17]. The method is useful for

circuit design modification and tuning. There is no restriction on the number of

faults and tolerance is not a problem in this method because the method targets all

actual component values. However, the method normally assumes that all circuit

nodes are accessible and thus it is not practical for modern IC diagnosis [15, 16]. In

addition, some parameter identification requires solving non-linear equations [13, 14],

which is computationally demanding especially for large-scale circuits. The parameter

identification method has thus become more of a topic of theoretical interest in circuit

diagnosis, in contrast to circuit analysis and circuit design. The only exception is

perhaps the optimization-based identification technique [17] that can have limited

tests for approximate, but optimized, component value calculation. The optimization￾based method will be discussed in the context of the neural network approach in

Chapter 3.

The fault verification method [18–39] is concerned with fault location of analogue

circuits with a small number of test nodes and a limited number of faults by using lin￾ear diagnosis equations. Indeed, modern highly integrated systems have very limited

external accessibility and normally only a few components become faulty simulta￾neously. Under the assumption that the number of faults is fewer than the number of

accessible nodes, the fault locations of a circuit can be determined by simply checking

the consistency of a set of linear equations. Thus, the SAT computation burden of

the method is small. The fault verification method is suitable for all types of fault,

and component values can also be determined after fault location. Tolerance effects

are, however, of concern in this method because fault-free components are assumed

to take their nominal values. The fault verification method has attracted considerable

attention, with the k-fault diagnosis approach [18–39] being widely investigated.

This chapter systematically introduces k-fault diagnosis theory and methods for

both linear and non-linear circuits as well as the derivative class-fault diagnosis

approach. We also give a general overview of recent research in fault diagnosis of

analogue circuits. Throughout the chapter, a unified discussion is adopted based on

the fault incremental circuit concept. In Section 1.2, we introduce the fault incremen￾tal circuit of linear circuits and discuss various k-fault diagnosis methods including

branch-, node- and cutset-fault diagnoses and various practical issues such as compo￾nent value determination and testability analysis and design. A class-fault diagnosis

theory without structural restrictions for fault location is introduced in Section 1.3,

which comprises both algebraic and topological classification methods. In Section 1.4,

the fault incremental circuit of non-linear circuits is constructed and a series of linear