Tài liệu Useful Modeling Techniques part 3 pptx

[ Team LiB ]

9.5 Useful System Tasks

In this section, we discuss the system tasks that are useful for a variety of purposes in

Verilog. We discuss system tasks [1] for file output, displaying hierarchy, strobing,

random number generation, memory initialization, and value change dump.

[1] Other system tasks such as $signed and $unsigned used for sign conversion are not

discussed in this book. For details, please refer to the "IEEE Standard Verilog Hardware

Description Language" document.

9.5.1 File Output

Output from Verilog normally goes to the standard output and the file verilog.log. It is

possible to redirect the output of Verilog to a chosen file.

Opening a file

A file can be opened with the system task $fopen.

Usage: $fopen("<name_of_file>"); [2]

[2] The "IEEE Standard Verilog Hardware Description Language" document provides

additional capabilities for $fopen. The $fopen syntax mentioned in this book is adequate

for most purposes. However, if you need additional capabilities, please refer to the "IEEE

Standard Verilog Hardware Description Language" document.

Usage: <file_handle> = $fopen("<name_of_file>");

The task $fopen returns a 32-bit value called a multichannel descriptor.[3] Only one bit is

set in a multichannel descriptor. The standard output has a multichannel descriptor with

the least significant bit (bit 0) set. Standard output is also called channel 0. The standard

output is always open. Each successive call to $fopen opens a new channel and returns a

32-bit descriptor with bit 1 set, bit 2 set, and so on, up to bit 30 set. Bit 31 is reserved.

The channel number corresponds to the individual bit set in the multichannel descriptor.

Example 9-9 illustrates the use of file descriptors.

[3] The "IEEE Standard Verilog Hardware Description Language" document provides a

method for opening up to 230 files by using a single-channel file descriptor. Please refer

to it for details.

Example 9-9 File Descriptors