Springer.Analysis.And.Design.Of.Resilient.VLSI.Circuits.Oct.2009.eBook-ELOHiM

Analysis and Design of Resilient VLSI Circuits

Rajesh Garg • Sunil P. Khatri

Analysis and Design

of Resilient VLSI Circuits

Mitigating Soft Errors and Process Variations

13

ISBN 978-1-4419-0930-5 e-ISBN 978-1-4419-0931-2

DOI 10.1007/978-1-4419-0931-2

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Library of Congress Control Number: 2009936000

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Rajesh Garg

6430 NE Alder St.

Apt. B

Hillsboro, OR 97124

USA

[email protected]

Sunil P. Khatri

Department of Electrical and Computer Engineering

Texas A & M University

214 Zachry Engineering Center

College Station, TX 77843-3128

USA

[email protected]

To,

Our families

-Rajesh and Sunil

Preface

This monograph is motivated by the challenges faced in designing reliable VLSI

systems in modern VLSI processes. The reliable operation of integrated circuits

(ICs) has become increasingly difficult to achieve in the deep submicron (DSM)

era. With continuously decreasing device feature sizes, combined with lower supply

voltages and higher operating frequencies, the noise immunity of VLSI circuits is

decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise

effects such as crosstalk, power supply variations, and radiation-induced soft errors.

Among these noise sources, soft errors (or error caused by radiation particle strikes)

have become an increasingly troublesome issue for memory arrays as well as com￾binational logic circuits. Also, in the DSM era, process variations are increasing at

a significant rate, making it more difficult to design reliable VLSI circuits. Hence, it

is important to efficiently design robust VLSI circuits that are resilient to radiation

particle strikes and process variations. The work presented in this research mono￾graph presents several analysis and design techniques with the goal of realizing

VLSI circuits, which are radiation and process variation tolerant.

This monograph consists of two parts. The first part proposes four analysis and

two design approaches to address radiation particle strikes. The analysis techniques

for the radiation particle strikes include: an approach to analytically determine the

pulse width and the pulse shape of a radiation-induced voltage glitch in combina￾tional circuits, a technique to model the dynamic stability of SRAMs, and a 3D

device-level analysis of the radiation tolerance of voltage scaled circuits. Experi￾mental results demonstrate that the proposed techniques for analyzing the effect of

radiation particle strikes in combinational circuits and SRAMs are fast and accu￾rate when compared with SPICE simulations. Therefore, these analysis approaches

can be easily integrated in a VLSI design flow to analyze the radiation tolerance

of ICs, to harden them early in the design flow. From 3D device-level analysis

of the radiation tolerance of voltage scaled circuits, several nonintuitive observa￾tions are made and correspondingly, a set of guidelines are proposed, which are

important to consider in order to realize radiation hardened circuits. In the first part

of this monograph, two circuit level hardening approaches are also presented to

harden combinational circuits against a radiation particle strike. These hardening

approaches significantly improve the tolerance of combinational circuits against low

and very high energy radiation particle strikes, respectively, with modest area and

delay overheads.

vii

viii Preface

The second part of this monograph addresses process variations. A technique is

developed to perform sensitizable statistical timing analysis of a circuit, and thereby

it improves the accuracy of timing analysis under process variations. Experimental

results demonstrate that this technique is able to significantly reduce the pessimism

due to two sources of inaccuracy, which plague current statistical static timing anal￾ysis (SSTA) tools. Two design approaches are also proposed to improve the process

variation tolerance of combinational circuits and voltage level shifters (which are

required in circuits with multiple interacting power supply domains), respectively.

The variation tolerant design approach for combinational circuits significantly im￾proves the resilience of these circuits to random process variations, with a reduction

in the worst case delay and with a low area penalty. The proposed voltage level

shifter is faster, requires lower dynamic power and area, has lower leakage currents,

and is more tolerant to process variations, compared with the best known previous

approach.

In summary, this monograph presents several analysis and design techniques

which significantly augment the existing body of knowledge in the area of resilient

VLSI circuit design.

Hillsboro, OR Rajesh Garg

College Station, TX Sunil P. Khatri

April 2009

Acknowledgements

The authors would like to gratefully acknowledge Dr. Nikhil Jayakumar, Kanupriya

Gulati, Charu Nagpal, and Gagandeep Mallarapu for their direct or indirect contri￾bution to the work presented in this monograph. The efforts of Dr. Nikhil Jayakumar,

who worked jointly on the diode clamping-based radiation hardening approach and

the sensitizable statistical timing analysis approach, are kindly appreciated. Work

on the analytical determination of radiation-induced pulse width and on the voltage

level shifter was performed jointly with Charu and Gagan, respectively. The insight￾ful comments of Dr. Peng Li, Dr. Hank Walker, Dr. Kevin Nowka, Dr. Gwan Choi,

and Dr. Krishna Narayanan are gratefully acknowledged.

ix

Contents

1 Introduction .................................................................... 1

1.1 Background and Motivation ............................................ 2

1.1.1 Radiation Particle Strikes ..................................... 2

1.1.2 Process Variations ............................................. 10

1.2 Monograph Overview ................................................... 12

1.3 Chapter Summary ....................................................... 15

References....................................................................... 15

Part I Soft Errors

2 Analytical Determination of Radiation-induced Pulse

Width in Combinational Circuits............................................ 21

2.1 Introduction.............................................................. 21

2.2 Related Previous Work .................................................. 23

2.3 Proposed Analytical Model for the Pulse Width

of Radiation-induced Voltage Glitch ................................... 24

2.3.1 Radiation Particle Strike at the Output of an Inverter........ 25

2.3.2 Classification of Radiation Particle Strikes................... 26

2.3.3 Overview of the Model for Determining

the Pulse Width of the Voltage Glitch ........................ 27

2.3.4 Derivation of the Proposed Model

for Determining the Pulse Width of the Voltage Glitch...... 29

2.4 Experimental Results.................................................... 35

2.5 Chapter Summary ....................................................... 39

References....................................................................... 39

3 Analytical Determination of the Radiation-induced Pulse Shape ........ 41

3.1 Introduction.............................................................. 41

3.2 Related Previous Work .................................................. 42

3.3 Proposed Analytical Model for the Shape

of Radiation-induced Voltage Glitch ................................... 43

xi

xii Contents

3.3.1 Overview of the Proposed Model for Determining

the Pulse Shape of the Voltage Glitch ........................ 44

3.3.2 Derivation of the Model for Determining

the Shape of the Radiation-induced Voltage Glitch .......... 46

3.4 Experimental Results.................................................... 53

3.5 Chapter Summary ....................................................... 57

References....................................................................... 57

4 Modeling Dynamic Stability of SRAMs in the Presence

of Radiation Particle Strikes ................................................. 59

4.1 Introduction.............................................................. 59

4.2 Related Previous Work .................................................. 60

4.3 Proposed Model for the Dynamic Stability of SRAMs

in the Presence of Radiation Particle Strikes........................... 61

4.3.1 Weak Coupling Mode Analysis............................... 63

4.3.2 Strong Feedback Mode Analysis ............................. 66

4.4 Experimental Results.................................................... 67

4.5 Chapter Summary ....................................................... 69

References....................................................................... 69

5 3D Simulation and Analysis of the Radiation Tolerance

of Voltage Scaled Digital Circuits............................................ 71

5.1 Introduction.............................................................. 71

5.2 Related Previous Work .................................................. 72

5.3 Simulation Setup ........................................................ 73

5.3.1 NMOS Device Modeling and Characterization .............. 75

5.4 Experimental Results.................................................... 76

5.5 Chapter Summary ....................................................... 84

References....................................................................... 85

6 Clamping Diode-based Radiation Tolerant Circuit Design Approach... 87

6.1 Introduction.............................................................. 87

6.2 Related Previous Work .................................................. 88

6.3 Proposed Clamping Diode-based Radiation Hardening ............... 89

6.3.1 Operation of Radiation-induced Voltage

Clamping Devices ............................................. 89

6.3.2 Critical Depth for a Gate ...................................... 92

6.3.3 Circuit Level Radiation Hardening ........................... 92

6.3.4 Alternative Circuit Level Radiation Hardening .............. 94

6.3.5 Final Circuit Selection......................................... 96

6.4 Experimental Results.................................................... 96

6.5 Chapter Summary .......................................................105

References.......................................................................107

Contents xiii

7 Split-output-based Radiation Tolerant Circuit Design Approach........109

7.1 Introduction..............................................................109

7.2 Related Previous Work ..................................................110

7.3 Proposed Split-output-based Radiation Hardening ....................110

7.3.1 Radiation Tolerant Standard Cell Design.....................110

7.3.2 Circuit Level Radiation Hardening ...........................115

7.3.3 Critical Charge for Radiation Hardened Circuits ............119

7.4 Experimental Results....................................................122

7.5 Chapter Summary .......................................................126

References.......................................................................127

Part II Process Variations

8 Sensitizable Statistical Timing Analysis.....................................131

8.1 Introduction..............................................................131

8.2 Related Previous Work ..................................................132

8.3 Proposed Sensitizable Statistical Timing Analysis Approach.........134

8.3.1 Phase 1: Finding Sensitizable Delay-critical

Vector Transitions .............................................134

8.3.2 Propagating Arrival Times ....................................135

8.3.3 Phase 2: Computing the Output Delay Distribution .........141

8.4 Experimental Results....................................................141

8.4.1 Determining the Number of Input Vector

Transitions N ..................................................148

8.5 Chapter Summary .......................................................150

References.......................................................................150

9 A Variation Tolerant Combinational Circuit Design

Approach Using Parallel Gates ..............................................153

9.1 Introduction..............................................................153

9.2 Related Previous Work ..................................................154

9.3 Process Variation Tolerant Combinational Circuit Design ............155

9.3.1 Process Variations .............................................155

9.3.2 Variation Tolerant Standard Cell Design .....................156

9.3.3 Variation Tolerant Combinational Circuits ...................159

9.4 Experimental Results....................................................160

9.5 Chapter Summary .......................................................169

References.......................................................................169

10 Process Variation Tolerant Single-supply True Voltage

Level Shifter ....................................................................173

10.1 Introduction..............................................................173

10.2 The Need for a Single-supply Voltage Level Shifter ..................174

10.3 Related Previous Work ..................................................176

10.4 Proposed Single-supply True Voltage Level Shifter ...................177

xiv Contents

10.5 Experimental Results....................................................180

10.5.1 Performance Comparison with Nominal

Parameters Value ..............................................181

10.5.2 Performance Comparison Under Process

and Temperature Variations ...................................182

10.5.3 Voltage Translation Range for SS-TVLS.....................183

10.5.4 Layout of SS-TVLS ...........................................184

10.6 Chapter Summary .......................................................186

References.......................................................................188

11 Conclusions and Future Directions..........................................189

References.......................................................................193

Sentaurus Related Code ...........................................................195

A.1 Code for 3D NMOS Device Creation Using

Sentaurus-Structure Editor Tool ........................................195

A.1.1 Code for Mixed-Level Simulation of a Radiation

Particle Strike Using Sentaurus-DEVICE ....................203

Index .................................................................................207

List of Figures

1.1 Charge deposition and collection by a radiation particle strike .......... 4

1.2 Current pulse model for a radiation particle strike plotted

for different values of Q, ’ and “ ....................................... 7

1.3 SER of an alpha processor for different technology nodes [4]........... 9

1.4 Variation in threshold voltage of devices for different

technology nodes ........................................................... 11

2.1 (a) Radiation-induced current injected at the output

of inverter INV1, (b) Voltage glitch at node a ............................ 25

2.2 Flowchart of the proposed model for pulse width calculation ........... 28

2.3 Voltage/current due to a radiation particle strike at node a

of INV1 of Fig. 2.1a........................................................ 32

3.1 Radiation-induced current injected at the output of inverter INV1 ...... 43

3.2 Flowchart of the proposed model for the shape of the

radiation-induced voltage glitch ........................................... 45

3.3 Radiation-induced voltage glitches obtained using

the proposed model and SPICE for different gates ....................... 54

3.4 Radiation-induced voltage glitch at 2X-INV1 ............................ 56

4.1 SRAM cell with noise current (access transistors are not shown) ....... 62

4.2 SRAM node voltages for the noise injected at node n2 .................. 63

4.3 Flowchart of the proposed model for SRAM cell stability ............... 64

4.4 Comparison of critical charge obtained using HSPICE

and the proposed model .................................................... 68

5.1 Inverter (INV) under consideration ........................................ 73

5.2 3D NMOS transistor of INV of Fig. 5.1 and its cross-section............ 75

5.3 NMOS device: ID vs. VDS plot for different VGS values.................. 76

5.4 Radiation-induced voltage transient at the output of 4

INV with VDD D 1V ...................................................... 77

5.5 Radiation-induced voltage transient at the output of 2

INV with VDD D 1V ...................................................... 77

xv

xvi List of Figures

5.6 Radiation-induced voltage transient at the output of 15

INV with VDD D 1V ...................................................... 78

5.7 Radiation-induced drain current of the NMOS transistor

of 4 INV with VDD D 1V ............................................... 78

5.8 Radiation-induced drain current of the NMOS transistor

of 2 INV with VDD D 1V ............................................... 79

5.9 Radiation-induced drain current of the NMOS transistor

of 15 INV with VDD D 1V ............................................. 79

5.10 Charge collected at the output of INV for different values .............. 80

5.11 Area of voltage glitch vs. VDD............................................ 80

5.12 Comparison of charge collected (Q) obtained from

the proposed model vs. 3D simulations ................................... 84

6.1 Diode-based radiation-induced voltage glitch clamping circuit.......... 89

6.2 Device-based radiation-induced voltage glitch clamping circuit......... 90

6.3 Layout of radiation-tolerant NAND2 gate (uses device

based clamping) ............................................................ 97

6.4 Output voltage waveform during a radiation event on output ............ 98

6.5 Output voltage waveform during a radiation event on protecting node .. 98

7.1 Design of an radiation tolerant inverter ...................................111

7.2 Radiation particle strike at out1p and out1n of INV1 of Fig. 7.1d ......114

7.3 Radiation tolerant gates ....................................................115

7.4 Modified regular gates......................................................116

7.5 Part of a circuit .............................................................118

7.6 Waveforms at nodes cp, cn, and d of Fig. 7.5b...........................119

7.7 Radiation tolerant flip-flop .................................................120

7.8 (a) Circuit under consideration, (b) Waveform at different nodes .......121

7.9 Area and delay overhead of our radiation hardening design

approach for different coverage............................................126

8.1 Arrival time propagation using a NAND2 gate ...........................137

8.2 Plot of arrival times at output of NAND2 gate calculated

through various means for the transition 00 ! 11........................139

8.3 Plot of arrival times at output of NAND2 gate calculated

through various means for the transition 11 ! 00........................139

8.4 Plot of arrival times at output of NOR2 gate calculated

through various means for the transition 00 ! 11........................140

8.5 Plot of arrival times at output of NOR2 gate calculated

through various means for the transition 11 ! 00........................140

8.6 Characterization of NAND2 delay for all input transitions

which cause a rising output. (a) 11 ! 00, (b) 11 ! 01,

and (c) 11 ! 10 ............................................................142

List of Figures xvii

8.7 Characterization of NAND2 delay for all input transitions

which cause a falling output. (a) 00 ! 11, (b) 01 ! 11,

and (c) 10 ! 11 ............................................................143

8.8 Delay histograms for (a) SSTA, (b) StatSense, and (c)

SPICE (for apex7).........................................................147

9.1 4 inverter implementations...............................................156

9.2 2 input NAND gate: (a) regular, (b) parallel ..............................157

9.3 Capacitance of various nodes: (a) regular inverter,

(b) parallel inverter .........................................................158

9.4 Results for 4 regular and parallel inverters: (a) standard

deviation of delay, (b) worst case delay, and (c) standard

deviation of output slew ...................................................160

9.5 Ratio of results of the proposed approach compared

with regular circuits for different values of P ............................164

9.6 Delay ,  C 3, and area ratio of the proposed approach

compared with regular circuits for different values of P

for area mapped (AM1) designs ...........................................166

9.7 Delay ,  C 3 and area ratio of the proposed approach

compared with regular circuits for different values of P

for DM1 designs............................................................167

9.8 Delay ,  C 3, and area ratio of the proposed approach

compared with regular circuits for different values of P

for DM2 designs............................................................168

10.1 Conventional voltage level shifter .........................................174

10.2 Multivoltage system using CVLS .........................................175

10.3 Multivoltage system using SS-TVLS......................................176

10.4 Novel single supply true voltage level shifter .............................178

10.5 Timing diagram for the proposed SS-TVLS ..............................178

10.6 Combination of an inverter and SS-VLS by Khan et al...................180

10.7 Delay of SS-TVLS: (a) rising, (b) falling .................................185

10.8 Power of SS-TVLS: (a) rising, (b) falling ................................186

10.9 Leakage current of SS-TVLS: (a) high, (b) low ..........................187

10.10 Layout of the proposed SS-TVLS .........................................187