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Blair-Chappell ffi rs V4 - 03/16/2012

PARALLEL PROGRAMMING

WITH INTELØ PARALLEL STUDIO XE

FOREWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvii

PART I AN INTRODUCTION TO PARALLELISM

CHAPTER 1 Parallelism Today . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

CHAPTER 2 An Overview of Parallel Studio XE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CHAPTER 3 Parallel Studio XE for the Impatient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PART II USING PARALLEL STUDIO XE

CHAPTER 4 Producing Optimized Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

CHAPTER 5 Writing Secure Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

CHAPTER 6 Where to Parallelize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

CHAPTER 7 Implementing Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

CHAPTER 8 Checking for Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

CHAPTER 9 Tuning Parallel Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

CHAPTER 10 Parallel Advisor–Driven Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

CHAPTER 11 Debugging Parallel Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

CHAPTER 12 Event-Based Analysis with VTune Amplifi er XE . . . . . . . . . . . . . . . . . . . 341

PART III CASE STUDIES

CHAPTER 13 The World’s First Sudoku “Thirty-Niner” . . . . . . . . . . . . . . . . . . . . . . . . . 377

CHAPTER 14 Nine Tips to Parallel-Programming Heaven . . . . . . . . . . . . . . . . . . . . . . 397

CHAPTER 15 Parallel Track Fitting in the CERN Collider . . . . . . . . . . . . . . . . . . . . . . . 419

CHAPTER 16 Parallelizing Legacy Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

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Blair-Chappell ffi rs V4 - 03/16/2012

Parallel Programming

with IntelØ Parallel Studio XE

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Blair-Chappell ffi rs V4 - 03/16/2012

Parallel Programming

with IntelØ Parallel Studio XE

Stephen Blair-Chappell

Andrew Stokes

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Parallel Programming with IntelØ Parallel Studio XE

Published by

John Wiley & Sons, Inc.

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Indianapolis, IN 46256

www.wiley.com

Copyright © 2012 by John Wiley & Sons, Inc., Indianapolis, Indiana

Published simultaneously in Canada

ISBN: 978-0-470-89165-0

ISBN: 978-1-118-22113-6 (ebk)

ISBN: 978-1-118-23488-4 (ebk)

ISBN: 978-1-118-25954-2 (ebk)

Manufactured in the United States of America

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Limit of Liability/Disclaimer of Warranty: The publisher and the author make no representations or warranties with

respect to the accuracy or completeness of the contents of this work and specifi cally disclaim all warranties, including

without limitation warranties of fi tness for a particular purpose. No warranty may be created or extended by sales or pro￾motional materials. The advice and strategies contained herein may not be suitable for every situation. This work is sold

with the understanding that the publisher is not engaged in rendering legal, accounting, or other professional services.

If professional assistance is required, the services of a competent professional person should be sought. Neither the pub￾lisher nor the author shall be liable for damages arising herefrom. The fact that an organization or Web site is referred to

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Trademarks: Wiley, the Wiley logo, Wrox, the Wrox logo, Programmer to Programmer, and related trade dress are trade￾marks or registered trademarks of John Wiley & Sons, Inc. and/or its affi liates, in the United States and other countries,

and may not be used without written permission. Intel is a registered trademark of Intel Corporation. All other trade￾marks are the property of their respective owners. John Wiley & Sons, Inc., is not associated with any product or vendor

mentioned in this book.

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ABOUT THE AUTHORS

STEPHEN BLAIR-CHAPPELL has been working for Intel in the Software and Services Group (SSG) for

the past 15 years. During his time with Intel, Stephen has worked on the compiler team as a devel￾oper and, more recently, as a technical consulting engineer helping users make the best use of the

Intel software tools. Prior to working with Intel, Stephen was managing director of the UK offi ce of

CAD-UL, a German-based compiler and debugger company. During his time at CAD-UL Stephen

was primarily responsible for technical support in the UK. Projects he worked on during that time

included the design and specifi cation of a graphical linker; the development and teaching of pro￾tected mode programming courses to programmers; and support to many varied companies in the

telecoms, automotive, and embedded industries.

Stephen fi rst studied electronics as a technician at Matthew Boulton Technical College, and later

studied Applied Software Engineering at Birmingham City University (BCU), where he also eventu￾ally taught. Outside work, Stephen is a regular contributor to the life of his local church, St Martin

in the Bull Ring, Birmingham, where he plays the organ, preaches, and leads the occasional service.

ANDREW STOKES is a retired lecturer in software and electronics at Birmingham City University

(BCU), UK. Prior to lecturing, Andrew was a software developer in the research and commercial

fi elds. He fi rst started software development in the 1980s at Cambridge University Engineering

Laboratory, where he worked on software for scanning electron microscopes. These software devel￾opments continued in the commercial fi eld, where he worked on graphical programs in support of a

Finite Element Analysis package.

During his time at BCU, Andrew developed many software simulation tools, including programs

for artifi cial neural network simulation, CPU simulation, processor design, code development tools,

and a PROLOG expert system. Andrew continues these software interests during retirement, with

a healthy interest in games programming, such as 3-D chess, where parallel programming is para￾mount. Away from computing, Andrew is a keen gardener and particularly likes the vibrant colors

of the typical English garden.

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ABOUT THE TECHNICAL EDITORS

KITTUR GANESH is a Senior Technical Consulting Engineer at Intel, providing consulting, sup￾port, and training for more than 7 years on various software products targeting Intel architecture.

Previously, for more than 6 years at Intel, Kittur designed and developed software primarily used

for fracturing design data of Intel chips. Prior to joining Intel more than 13 years ago, Kittur was

involved in developing commercial software in the EDA industry for more than 10 years. Kittur has

a M.S. (Computer Science), M.S. (Industrial Engineering) and a B.S. (Mechanical Engineering).

PABLO HALPERN is a Senior Software Engineer at Intel Corporation, working in the parallel runtime

libraries group. He is a member of the C++ Standards Committee and helped produce the recent

C++11 revision of the standard. Pablo is the author of the well-received book, The C++ Standard

Library from Scratch and a coauthor of the paper, Reducers and Other Cilk++ Hyperobjects, which

was named best paper at ACM SPAA in 2009. He has more than three decades of experience in the

software industry, with expertise in C++, language and compiler design, large-scale development

and testing, and network management protocols. During this time, he has developed and taught

both beginning and advanced courses on C++ programming. He currently lives in New Hampshire

with his wife and two children.

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CREDITS

ACQUISITIONS EDITOR

Paul Reese

PROJECT EDITOR

John Sleeva

TECHNICAL EDITORS

Kittur Ganesh

Pablo Halpern

PRODUCTION EDITOR

Daniel Scribner

COPY EDITOR

Kim Cofer

EDITORIAL MANAGER

Mary Beth Wakefi eld

FREELANCER EDITORIAL MANAGER

Rosemarie Graham

ASSOCIATE DIRECTOR OF MARKETING

David Mayhew

MARKETING MANAGER

Ashley Zurcher

BUSINESS MANAGER

Amy Knies

PRODUCTION MANAGER

Tim Tate

VICE PRESIDENT AND EXECUTIVE GROUP

PUBLISHER

Richard Swadley

VICE PRESIDENT AND EXECUTIVE PUBLISHER

Neil Edde

ASSOCIATE PUBLISHER

Jim Minatel

PROJECT COORDINATOR, COVER

Katie Crocker

PROOFREADER

Mark Steven Long

INDEXER

Robert Swanson

COVER DESIGNER

LeAndra Young

COVER IMAGE

© Orlando Rosu / iStockPhoto

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ACKNOWLEDGMENTS

FIRST, WE WOULD LIKE TO THANK our families and friends for being supportive and patient while we

wrote this book.

We want to thank everyone at Wrox for giving us this opportunity. Thanks to Paul Reese, the

acquisitions editor, who fi rst asked us to write this book; to John Sleeva, the project editor, without

whose help and guidance this book would not have made it to completion; to Kim Cofer, the copy

editor; to Kittur Ganesh and Pablo Halpern, the technical editors, whose timely advice was a great

help; to Gastón Hillar, who assisted by providing further technical reviews; and to the all the people

in the graphics department, for your work on all the fi gures.

We’d like to say a special “thank you” to those who have contributed to the book, especially to

Mark Davis, who wrote Chapter 10, “Parallel Advisor–Driven Design,” and to Fred Tedeschi, who

wrote Chapter 11, “Debugging Parallel Applications.”

We also want to thank those who allowed us to write about their experiences in the case studies.

Thanks to Lars Peters Endresen and Håvard Graff for their work in Chapter 13, “The World’s First

Sudoku ‘Thirty-Niner’”; to Dr. Yann Golanski, for his input into Chapter 14, “Nine Tips to Parallel￾Programming Heaven”; and to Hans Pabst, for his help with Chapter 15, “Parallel Track Fitting in

the CERN Collider.”

Our appreciation also goes to the many colleagues from Intel who tirelessly reviewed different

chapters — in particular, Levent Akyil, Bernth Andersson, Julian Horn, Martyn Corden, Maxym

Dmytrychenko, Max Domeika, Hubert Haberstock, Markus Metzger, Mark Sabahi, and Thomas

Zipplies.

Finally, thanks to James Reinders, who encouraged the writing of this book and has been kind

enough to provide the Foreword.

— Stephen Blair-Chappell

Andrew Stokes

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Blair-Chappell ftoc V3 - 03/16/2012

CONTENTS

FOREWORD xxv

INTRODUCTION xxvii

PART I: AN INTRODUCTION TO PARALLELISM

CHAPTER 1: PARALLELISM TODAY 3

The Arrival of Parallelism 3

The Power Density Race 3

The Emergence of Multi-Core and Many-Core Computing 4

The Top Six Challenges 7

Legacy Code 7

Tools 7

Education 8

Fear of Many-Core Computing 8

Maintainability 8

Return on Investment 9

Parallelism and the Programmer 9

Types of Parallelism 9

Intel’s Family of Parallel Models 10

Cilk Plus and Threading Building Blocks 10

Domain-Specifi c Libraries 11

Established Standards 11

Research and Development 11

Choosing the Right Parallel Constructs 11

High-Level vs. Low-Level Constructs 12

Data Parallelism vs. General Parallelism 12

Examples of Mixing and Matching Parallel Constructs 12

Parallel Programming Errors 15

Data Races 15

Determinacy Races 15

Deadlocks 16

Poor Load Balancing 17

Threading/Tasking Overhead 17

Synchronization Overhead 17

Memory Errors 17

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