Nano-CMOS circuit and physical design

NANO-CMOS CIRCUIT

AND PHYSICAL DESIGN

NANO-CMOS CIRCUIT

AND PHYSICAL DESIGN

Ban P. Wong

NVIDIA

Anurag Mittal

Virage Logic, Inc.

Yu Cao

University of California–Berkeley

Greg Starr

Xilinx

A JOHN WILEY & SONS, INC., PUBLICATION

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Library of Congress Cataloging-in-Publication Data:

Nano-CMOS circuit and physical design / Ban P. Wong ... [et al.].

p. cm.

Includes bibliographical references and index.

ISBN 0-471-46610-7 (cloth)

1. Metal oxide semiconductors, Complementary–Design and construction. 2.

Integrated circuits–Design and construction. I. Wong, Ban P., 1953–

TK7871.99.M44N36 2004

621.39

732–dc22 2004002212

Printed in the United States of America.

10 9 8 7 6 5 4 3 2 1

CONTENTS

FOREWORD xiii

PREFACE xv

1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS 1

1.1 Design Methodology in the Nano-CMOS Era 1

1.2 Innovations Needed to Continue Performance

Scaling 3

1.3 Overview of Sub-100-nm Scaling Challenges

and Subwavelength Optical Lithography 6

1.3.1 Back-End-of-Line Challenges (Metallization) 6

1.3.2 Front-End-of-Line Challenges (Transistors) 12

1.4 Process Control and Reliability 15

1.5 Lithographic Issues and Mask Data Explosion 16

1.6 New Breed of Circuit and Physical Design

Engineers 17

1.7 Modeling Challenges 17

1.8 Need for Design Methodology Changes 19

1.9 Summary 21

References 21

v

vi CONTENTS

PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH

OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION,

ISSUES, AND SOLUTIONS

2 CMOS DEVICE AND PROCESS TECHNOLOGY 24

2.1 Equipment Requirements for Front-End Processing 24

2.1.1 Technical Background 24

2.1.2 Gate Dielectric Scaling 26

2.1.3 Strain Engineering 33

2.1.4 Rapid Thermal Processing Technology 34

2.2 Front-End-Device Problems in CMOS Scaling 41

2.2.1 CMOS Scaling Challenges 41

2.2.2 Quantum Effects Model 43

2.2.3 Polysilicon Gate Depletion Effects 45

2.2.4 Metal Gate Electrodes 48

2.2.5 Direct-Tunneling Gate Leakage 49

2.2.6 Parasitic Capacitance 52

2.2.7 Reliability Concerns 56

2.3 Back-End-of-Line Technology 58

2.3.1 Interconnect Scaling 59

2.3.2 Copper Wire Technology 61

2.3.3 Low-κ Dielectric Challenges 64

2.3.4 Future Global Interconnect Technology 65

References 66

3 THEORY AND PRACTICALITIES OF

SUBWAVELENGTH OPTICAL LITHOGRAPHY 73

3.1 Introduction and Simple Imaging Theory 73

3.2 Challenges for the 100-nm Node 76

3.2.1 κ-Factor for the 100-nm Node 77

3.2.2 Significant Process Variations 78

3.2.3 Impact of Low-κ Imaging on Process

Sensitivities 82

3.2.4 Low-κ Imaging and Impact on Depth

of Focus 83

3.2.5 Low-κ Imaging and Exposure Tolerance 84

3.2.6 Low-κ Imaging and Impact on Mask Error

Enhancement Factor 84

3.2.7 Low-κ Imaging and Sensitivity to Aberrations 86

CONTENTS vii

3.2.8 Low-κ Imaging and CD Variation as a Function

of Pitch 86

3.2.9 Low-κ Imaging and Corner Rounding Radius 89

3.3 Resolution Enhancement Techniques: Physics 91

3.3.1 Specialized Illumination Patterns 92

3.3.2 Optical Proximity Corrections 94

3.3.3 Subresolution Assist Features 101

3.3.4 Alternating Phase-Shift Masks 103

3.4 Physical Design Style Impact on RET and OPC Complexity 107

3.4.1 Specialized Illumination Conditions 108

3.4.2 Two-Dimensional Layouts 111

3.4.3 Alternating Phase-Shift Masks 114

3.4.4 Mask Costs 118

3.5 The Road Ahead: Future Lithographic Technologies 121

3.5.1 The Evolutionary Path: 157-nm Lithography 121

3.5.2 Still Evolutionary: Immersion Lithography 122

3.5.3 Quantum Leap: EUV Lithography 124

3.5.4 Particle Beam Lithography 126

3.5.5 Direct-Write Electron Beam Tools 126

References 130

PART II PROCESS SCALING IMPACT ON DESIGN

4 MIXED-SIGNAL CIRCUIT DESIGN 134

4.1 Introduction 134

4.2 Design Considerations 134

4.3 Device Modeling 135

4.4 Passive Components 142

4.5 Design Methodology 146

4.5.1 Benchmark Circuits 146

4.5.2 Design Using Thin Oxide Devices 146

4.5.3 Design Using Thick Oxide Devices 148

4.6 Low-Voltage Techniques 150

4.6.1 Current Mirrors 150

4.6.2 Input Stages 152

4.6.3 Output Stages 153

4.6.4 Bandgap References 154

4.7 Design Procedures 155

4.8 Electrostatic Discharge Protection 157

viii CONTENTS

4.8.1 Multiple-Supply Concerns 157

4.9 Noise Isolation 159

4.9.1 Guard Ring Structures 159

4.9.2 Isolated NMOS Devices 161

4.9.3 Epitaxial Material versus Bulk Silicon 161

4.10 Decoupling 162

4.11 Power Busing 166

4.12 Integration Problems 167

4.12.1 Corner Regions 167

4.12.2 Neighboring Circuitry 167

4.13 Summary 168

References 168

5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN 172

5.1 Introduction 172

5.2 ESD Standards and Models 173

5.3 ESD Protection Design 173

5.3.1 ESD Protection Scheme 173

5.3.2 Turn-on Uniformity of ESD Protection

Devices 175

5.3.3 ESD Implantation and Silicide Blocking 177

5.3.4 ESD Protection Guidelines 178

5.4 Low-C ESD Protection Design for High-Speed I/O 178

5.4.1 ESD Protection for High-Speed I/O or Analog Pins 178

5.4.2 Low-C ESD Protection Design 180

5.4.3 Input Capacitance Calculations 183

5.4.4 ESD Robustness 185

5.4.5 Turn-on Verification 186

5.5 ESD Protection Design for Mixed-Voltage I/O 190

5.5.1 Mixed-Voltage I/O Interfaces 190

5.5.2 ESD Concerns for Mixed-Voltage I/O Interfaces 191

5.5.3 ESD Protection Device for a Mixed-Voltage I/O

Interface 192

5.5.4 ESD Protection Circuit Design for a Mixed-Voltage

I/O Interface 195

5.5.5 ESD Robustness 198

5.5.6 Turn-on Verification 199

5.6 SCR Devices for ESD Protection 200

5.6.1 Turn-on Mechanism of SCR Devices 201

CONTENTS ix

5.6.2 SCR-Based Devices for CMOS On-Chip ESD

Protection 202

5.6.3 SCR Latch-up Engineering 210

5.7 Summary 212

References 213

6 INPUT/OUTPUT DESIGN 220

6.1 Introduction 220

6.2 I/O Standards 221

6.3 Signal Transfer 222

6.3.1 Single-Ended Buffers 223

6.3.2 Differential Buffers 223

6.4 ESD Protection 227

6.5 I/O Switching Noise 228

6.6 Termination 232

6.7 Impedance Matching 234

6.8 Preemphasis 235

6.9 Equalization 237

6.10 Conclusion 238

References 239

7 DRAM 241

7.1 Introduction 241

7.2 DRAM Basics 241

7.3 Scaling the Capacitor 245

7.4 Scaling the Array Transistor 247

7.5 Scaling the Sense Amplifier 249

7.6 Summary 253

References 253

8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP

INTERCONNECTS 255

8.1 Introduction 255

8.1.1 Interconnect Figures of Merit 258

8.2 Interconnect Parasitics Extraction 259

8.2.1 Circuit Representation of Interconnects 260

8.2.2 RC Extraction 263

8.2.3 Inductance Extraction 267

x CONTENTS

8.3 Signal Integrity Analysis 271

8.3.1 Interconnect Driver Models 272

8.3.2 RC Interconnect Analysis 274

8.3.3 RLC Interconnect Analysis 277

8.3.4 Noise-Aware Timing Analysis 281

8.4 Design Solutions for Signal Integrity 283

8.4.1 Physical Design Techniques 284

8.4.2 Circuit Techniques 288

8.5 Summary 293

References 294

9 ULTRALOW POWER CIRCUIT DESIGN 298

9.1 Introduction 298

9.2 Design-Time Low-Power Techniques 300

9.2.1 System- and Architecture-Level Design-Time

Techniques 300

9.2.2 Circuit-Level Design-Time Techniques 300

9.2.3 Memory Techniques at Design Time 305

9.3 Run-Time Low-Power Techniques 311

9.3.1 System- and Architecture-Level Run-Time

Techniques 311

9.3.2 Circuit-Level Run-Time Techniques 313

9.3.3 Memory Techniques at Run Time 316

9.4 Technology Innovations for Low-Power Design 320

9.4.1 Novel Device Technologies 320

9.4.2 Assembly Technology Innovations 321

9.5 Perspectives for Future Ultralow-Power Design 321

9.5.1 Subthreshold Circuit Operation 322

9.5.2 Fault-Tolerant Design 322

9.5.3 Asynchronous versus Synchronous Design 323

9.5.4 Gate-Induced Leakage Suppression Schemes 323

References 324

PART III IMPACT OF PHYSICAL DESIGN ON

MANUFACTURING/YIELD AND PERFORMANCE

10 DESIGN FOR MANUFACTURABILITY 331

10.1 Introduction 331

10.2 Comparison of Optimal and Suboptimal Layouts 332

CONTENTS xi

10.3 Global Route DFM 338

10.4 Analog DFM 339

10.5 Some Rules of Thumb 341

10.6 Summary 342

References 342

11 DESIGN FOR VARIABILITY 343

11.1 Impact of Variations on Future Design 343

11.1.1 Parametric Variations in Circuit Design 343

11.1.2 Impact on Circuit Performance 345

11.2 Strategies to Mitigate Impact Due to Variations 347

11.2.1 Clock Distribution Strategies to Minimize Skew 347

11.2.2 SRAM Techniques to Deal with Variations 351

11.2.3 Analog Strategies to Deal with Variations 361

11.2.4 Digital Circuit Strategies to Deal

with Variations 370

11.3 Corner Modeling Methodology for Nano-CMOS

Processes 376

11.3.1 Need for Statistical Models 376

11.3.2 Statistical Model Use 378

11.4 New Features of the BSIM4 Model 381

11.4.1 Halo/Pocket Implant 381

11.4.2 Gate-Induced Drain Leakage and Gate Direct

Tunneling 382

11.4.3 Modeling Challenges 383

11.4.4 Model-Specific Issues 384

11.4.5 Model Summary 385

11.5 Summary 385

References 385

INDEX 389

FOREWORD

Relentless assaults on the frontiers of CMOS technology over several decades

have produced a marvel of a technology. The world we live in has been changed

by complex integrated circuits now containing a billion transistors with line

widths of less than 100 nm, fabricated in plants costing several billion dollars.

This microelectronics revolution was made possible only through the dedication

and ingenuity of many specialized experts with detailed knowledge of their crafts.

Yet IC designers, device integrators, and process engineers have always recog￾nized the benefits of a broad understanding of different aspects of IC technology

and have combated the compartmentalization of knowledge through continuing

learning. For IC designers, a good understanding of the underlying physical con￾straints of device, interconnect, and manufacturing is crucial for fully achieving

the product values attainable. For technology developers, knowing the impact of

technology on advanced designs provides the necessary foundation for making

sound technological decisions.

While the need to acquire knowledge in the neighboring field has always

existed, it has grown in recent years for several reasons. The pace of new tech￾nology introduction and the rate of rise of circuit speed increased significantly

beyond the historical rates of the previous two decades. This accelerated pace

may or may not be sustained for long; nevertheless, there is now a larger body

of new knowledge that awaits engineers to learn and use than before. A second

reason is that as technology scaling becomes more difficult, trade-offs such as

those between leakage and performance and between line width and variability

must, more than ever, be made judiciously with careful consideration of design,

device, and manufacturing. Finally, a large and increasing number of engineers

xiii

xiv FOREWORD

work for companies that specialize in either design or manufacturing (i.e., com￾panies without fabrication facilities or silicon foundries). These engineers face

greater challenges in seeing the complete picture than do those working for

integrated IC companies.

There are many books devoted to either silicon process technology or IC

design, but few that give a comprehensive view of the current status of both. It

is in this area of integration of nanometer processes, device manufacturability,

advanced circuit design, and related physical implementation that this book adds

the most value. It starts with a section of three chapters on recent and future

trends in devices and processing and continues through a second section of six

chapters describing design issues, with special attention paid to the interactions

between technology and design, such as signal integrity and interconnects as well

as practical solutions. The third and final section addresses the impact of design

on yield or design for manufacturability.

This book is for both IC designers and technologists who want a convenient

and up-to-date reference written by expert practitioners of the industry. In IC

technology there are still many more new territories to be pioneered and new

vistas to be discovered. This book is a good addition to our travel bags!

CHENMING HU

Taiwan Semiconductor Manufacturing Company

and the University of California–Berkeley

January 2004

PREFACE

In 1965, Gordon Moore formulated his now famous Moore’s law, which became

the catalyst for advancements in the semiconductor industry. The semiconductor

industry has brought us the sub-100-nm era with all the advancements we see

today. With these advancements come difficulties in process control and sub￾sequent challenges to circuit and physical design. As a result, the degrees of

freedom in design methodology are fast shrinking and will require a revolution￾ary change in the way we put together chips that are not only functional but also

meet the design objectives and are high yielding.

However, the explosive growth of semiconductor models developed in the

absence of fabrication facilities has resulted in the isolation of process/device

engineers from circuit design engineers, leading to some lack of understanding

of the impact of their designs upon manufacturability, yield, and performance,

due to the fundamental limitations of technology and device physics. As we

enter the nano-CMOS era, knowing how to traverse these issues is critical to

the success of products and companies. These communities of engineers must

work together to fill each other’s knowledge gaps, which are ever widening as

we travel down the road of dimensional scaling. Only by doing this can goals

be realized.

While faced with these issues during the course of our duties, we could find no

book that addresses them in a single bound volume. The information exists in bits

and pieces and mostly locked up in the minds of experts, some of whom we have

consulted in the course of our jobs. This book is an attempt to provide a seamless

entity that talks about these interactions and their impact on manufacturability,

yield, and performance. It provides practical guidelines to help designers avoid

some of the pitfalls inherent in advanced semiconductor processes as well as the

xv

xvi PREFACE

strongly needed bridge from physical and circuit design to fabrication processing,

manufacturability, and yield. The concepts we present in this text are extremely

significant, especially as technology moves into the nano-CMOS feature sizes.

The book is organized into three parts. In the first part we provide detailed

descriptions of the deep-submicron processes to help designers understand the

issues associated with them and to provide more insight into the limitations

brought about by dimensional scaling. In the second part we provide an overview

of the impact of process scaling on circuit design and physical implementation.

In the final part we cover issues concerning manufacturability and yield and

provide guidance to ensure that a part is manufacturable and meets the yield and

performance targets.

Chapter 1 provides an overview of the issues designers face in the deep￾submicron processes. This chapter provides a framework for the rest of the book.

Part I contains Chapters 2 and 3. In Chapter 2 we review the current status and

possible future solutions of FEOL and BEOL processing systems for 90 nm

and below. The FEOL section deals with gate dielectric and strain engineering

developments, including related equipment issues. It also provides an in-depth

discussion of CMOS scaling issues such as gate tunneling and NBTI. In the BEOL

section we discuss local and global interconnect scaling, copper wire develop￾ment, and low-κ interlayer dielectric challenges along with integration schemes

such as dual damascene. Chapter 3 is a tutorial on optical lithography which

encompasses the physics and theory of operation, including issues associated

with advanced processes and corresponding solutions.

Part II consists of Chapters 4 through 9. In Chapter 4 we provide a brief

overview of design issues facing mixed-signal circuits and guidance for avoiding

some of the pitfalls associated with designing circuits for advanced processes. In

Chapter 5 we provide an overview of the ESD issues designers face in the creation

of complex systems on a chip. Issues such as multiple supply protection are cov￾ered in detail to equip designers in the evaluation of specific ESD requirements.

The latest SCR structures are also included as yet another option for developing

an ESD protection strategy. Chapter 6 outlines the current trends in I/O buffer

design. An overview of the various I/O specifications is provided along with

current trends for implementing designs. Power busing issues and simultaneous

switching noise issues are discussed at length to illustrate the importance of devel￾oping the I/O power bus scheme up front. On-die decoupling is also discussed at

length, as this is becoming a key feature required to meet high-speed interface

specifications. Chapter 7 takes the reader through the basics of DRAM design and

then goes into the techniques to successfully scale the storage capacitor, access

transistor, and sense amplifier into nano-CMOS processes. Chapter 8 focuses on

signal integrity analysis and design solutions for on-chip interconnects. First, effi￾cient parasitics extraction techniques are presented, with particular emphasis on

inductance issues. Then analytical approaches for signal timing, crosstalk noise,

and waveform integrity analysis are discussed. In the last part of the chapter we

investigate physical and circuit design solutions to improve signal integrity in

high-speed signaling. Chapter 9 provides a comprehensive overview of existing