Low-power processors and systems on chips

LOW-POWER PROCESSORS

AND SYSTEMS ON CHIPS

Christian Piguet

A CRC title, part of the Taylor & Francis imprint, a member of the

Taylor & Francis Group, the academic division of T&F Informa plc.

Boca Raton London New York

CSEM

Neuch^

atel, Switzerland

Copyright © 2006 Taylor & Francis Group, LLC

This material was previously published in Low Power Electronics Design. © CRC Press LLC 2004.

Published in 2006 by

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© 2006 by Taylor & Francis Group, LLC

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10 9 876 5 4321

International Standard Book Number-10: 0-8493-6700-X (Hardcover)

International Standard Book Number-13: 978-0-8493-6700-7 (Hardcover)

Library of Congress Card Number 2005050175

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Library of Congress Cataloging-in-Publication Data

Piguet, Christian.

Low-power processors and systems on chips / Christian Piguet.

p. cm.

Includes bibliographical references and index.

ISBN 0-8493-6700-X (alk. paper)

1.Microprocessors – Power supply. 2. Systems on a chip. 3. Low voltage integrated circuits. I. Title.

TK7895.M5P54 2005

621.39’16—dc22 2005050175

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v

Preface

Purpose and Background

The present book is a part of the book “Low-Power Electronics Design,” edited by Christian Piguet,

published in November 2004. It contains only the chapters that describe the design of low-power

processors and systems-on-chips from microprocessors, DSP cores, reconfigurable processors, memories,

systems-on-chip issues, applications such as ad hoc networks and finally embedded software. All the

other chapters, describing microelectronics technologies, transistor models, logic circuits and CAD tools,

are also included in another smaller book entitled “Low-Power CMOS Circuits: Technology, Logic Design

and CAD Tools.”

The goal of the present book “Low-Power Processors and Systems on Chips” is to cover all the aspects

of the design of low-power microprocessors in deep submicron technologies. Today, the power consump￾tion of microprocessors is considered as one of the most important problems for high-performance chips

as well as for portable devices. For the latter, it is due to the limited cell battery lifetime, while it is the

chip cooling for the first case. As a result, for any chip design, power consumption has to be taken into

account very seriously. Before 1993–1994, only speed and silicon area were important in the design of

integrated circuits, and power consumption was not an issue. Just after, it was recognized that power

consumption has to be taken into account as a main design parameter. Many papers and books were

written to describe all the first design methodologies to save power limited to circuit design. However,

today, we have to cope with many new problems implied by very deep submicron technologies, such as

leakage power, interconnect delays and robustness.

Today, we are close to designing one billion transistor microprocessor chips, down to 0.10 µm and

below, supplied at less than half a volt and working at some GHz. This is due to an unexpected evolution

of the microelectronics technologies and to very innovative microprocessor architectures. This evolution

is not yet at its end, so the next decade will also see some spectacular improvements in the design of

microprocessor circuits. However, it is sure that the microprocessor architecture evolution is not always

a revolution, but as pointed out by:

“I was greatly amused few years ago — when companies were introducing pipelined microprocessors

— to learn that RISC technology enabled pipelining. That this could be responsible for pipelining,

which has existed for more than 30 years, illustrates the amnesia present in computer engineering”

Michael J. Flynn

Organization

The first part of the proposed book starts with a chapter about the design of low-power microprocessors

regarding the technology variations. The next three chapters present the design of Digital Signal Proces￾6700_C000.fm Page v Thursday, July 14, 2005 12:03 PM

Copyright © 2006 Taylor & Francis Group, LLC

vi

sors (DSP) for embedded applications. They have to provide huge power computation as well as very

small power consumption. So many different DSP architectures have been proposed, well adapted to

some specific DSP algorithms, working in cooperation with hardware accelerators or based on reconfig￾urable hardware. Asynchronous design for microprocessors is also proposed to reduce power consump￾tion. In wireless communication, low-power baseband processors are a key issue for portable devices.

However, a significant part of the power consumption is due to program and data memories, and the

last three chapters of this first part present some techniques to reduce dynamic and static power at the

electrical level as well as at the system level while using cache memories or specific memory organization.

The second part of the book is a set of chapters describing several aspects of low-power systems on

chips (SoCs). They include hardware and embedded software aspects, such as operating systems (OS),

data storage in an efficient way and networks on chips. The next chapters present some applications

requiring very low power SoCs, such as ad hoc networks with very low-power radios as well as routing

strategies and sensing and actuation devices.

The third part of the book presents issues about embedded software, i.e., application software and

compilers. The development tools including compilers, retargetable compilers, and coverification tools

are presented in details.

The key benefits for readers will be this complete picture of what is done today for reducing power

for microprocessors, DSP cores, memories, systems on chips, and embedded software.

Locating Your Topic

Several avenues are available to access desired information. A complete table of contents is presented at

the front of the book. Each of the chapter is also preceded with an individual table of contents. Each

contributed chapter contains comprehensive references including books, journal and magazine papers,

and sometimes Web pointers.

Acknowledgments

The value of this book is completely based on the many excellent contributions of experts. I am very

grateful to them, as they spent a lot of time writing excellent texts without any compensation. Their sole

motivation was to provide readers excellent contributions. I would like to thank all these authors, as I

am sure this book will be a very good text for many readers and students interested in low-power design.

I am indebted to Prof. Vojin G. Oklobjzija for asking me to edit this book and trusting me with this

project. I would also like to thank Nora Konopka and Allison Taub of CRC Press for their excellent work

in putting all this material in the present form. It is the work of all that made this book.

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vii

The Editor

Christian Piguet was born in Nyon, Switzerland, on January 18, 1951. He

received the M. S. and Ph. D. degrees in Electrical Engineering from the

Ecole Polytechnique Fédérale de Lausanne, Switzerland in 1974 and 1981,

respectively.

He joined the Centre Electronique Horloger S.A., Neuchâtel, Switzer￾land, in 1974. He worked on CMOS digital integrated circuits for the

watch industry, on low-power embedded microprocessors as well as on

CAD tools based on a gate matrix approach. He is now Head of the Ultra￾Low-Power Sector at the CSEM Centre Suisse d’Electronique et de Micro￾technique S.A., Neuchâtel, Switzerland. He is presently involved in the

design and management of low-power and high-speed integrated circuits

in CMOS technology. His main interests include the design of very low￾power microprocessors and DSPs, low-power standard cell libraries, gated

clock and low-power techniques as well as asynchronous design.

He is Professor at the Ecole Polytechnique Fédérale Lausanne (EPFL), Switzerland, and also lectures

in VLSI and microprocessor design at the University of Neuchâtel, Switzerland and in the ALaRI master

program at the University of Lugano, Switzerland. He is also a lecturer for many postgraduates courses

in low-power design.

Christian Piguet holds about 30 patents in digital design, microprocessors and watch systems. He is

author and coauthor of more than 170 publications in technical journals and of books and book chapters

in low-power digital design. He has served as reviewer for many technical journals. He also served as

Guest Editor for the July 1996 JSSC Issue. He is a member of steering and program committees of

numerous conferences and has served as Program Chairman of PATMOS’95 in Oldenburg, Germany,

co-chairman at FTFC’99 in Paris, Chairman of the ACiD’2001 Workshop in Neuchâtel, Co-Chair of

VLSI-SOC 2001 in Montpellier and Co-Chair of ISLPED 2002 in Monterey. He was Chairman of the

PATMOS executive committee during 2002. He was Low-Power Topic Chair at DATE 2004 and 2005.

Christian Piguet, CSEM SA, Jaquet-Droz 1, 2000 Neuchâtel, Switzerland

[email protected]

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Contents

I Low-Power Processors and Memories

1 Techniques for Power and Process Variation Minimization..........................................1-1

Lawrence T. Clark and Vivek De

2 Low-Power DSPs................................................................................................................2-1

Ingrid Verbauwhede

3 Energy-Efficient Reconfigurable Processors....................................................................3-1

Raphaël David, Sébastien Pillement, and Olivier Sentieys

4 Macgic, a Low-Power Reconfigurable DSP......................................................................4-1

Flavio Rampogna, Pierre-David Pfister, Claude Arm, Patrick Volet,

Jean-Marc Masgonty, and Christian Piguet

5 Low-Power Asynchronous Processors .............................................................................5-1

Kamel Slimani, Joao Fragoso, Mohammed Es Sahliene, Laurent Fesquet,

and Marc Renaudin

6 Low-Power Baseband Processors for Communications.................................................6-1

Dake Liu and Eric Tell

7 Stand-By Power Reduction for SRAM Memories ...........................................................7-1

Stefan Cserveny, Jean-Marc Masgonty, and Christian Piguet

8 Low-Power Cache Design..................................................................................................8-1

Vasily G. Moshnyaga and Koji Inoue

9 Memory Organization for Low-Energy Embedded Systems .........................................9-1

Alberto Macii

II Low-Power Systems on Chips

10 Power–Performance Trade-Offs in Design of SoCs......................................................10-1

Victor Zyuban and Philip Strenski

11 Low-Power SoC with Power-Aware Operating Systems Generation...........................11-1

Sungjoo Yoo, Aimen Bouchhima, Wander Cesario, Ahmed A. Jerraya,

and Lovic Gauthier

12 Low-Power Data Storage and Communication for SoC...............................................12-1

Miguel Miranda, Erik Brockmeyer, Tycho van Meeuwen, Cedric Ghez,

and Francky Catthoor

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xiv

13 Networks on Chips: Energy-Efficient Design of SoC Interconnect.............................13-1

Luca Benini, Terry Tao Ye, and Giovanni de Micheli

14 Highly Integrated Ultra-Low Power RF Transceivers for Wireless

Sensor Networks..............................................................................................................14-1

Brian P. Otis, Yuen Hui Chee, Richard Lu, Nathan M. Pletcher,

Jan M. Rabaey, and Simone Gambini

15 Power-Aware On-Demand Routing Protocols for Mobile Ad Hoc Networks ...........15-1

Morteza Maleki and Massoud Pedram

16 Modeling Computational, Sensing, and Actuation Surfaces........................................16-1

Phillip Stanley-Marbell, Diana Marculescu, Radu Marculescu,

and Pradeep K. Khosla

III Embedded Software

17 Low-Power Software Techniques....................................................................................17-1

Catherine H. Gebotys

18 Low-Power/Energy Compiler Optimizations................................................................18-1

Ulrich Kremer

19 Design of Low-Power Processor Cores Using a Retargetable Tool Flow ....................19-1

Gert Goossens, Peter Dytrych, and Dirk Lanneer

20 Recent Advances in Low-Power Design and Functional Coverification

Automation from the Earliest System-Level Design Stages.........................................20-1

Thierry J.-F. Omnès, Youcef Bouchebaba, Chidamber Kulkarni,

and Fabien Coelho

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ix

Contributors

Claude Arm

CSEM

Neuchâtel, Switzerland

Luca Benini

University of Bologna

Bologna, Italy

Youcef Bouchebaba

University of Nantes

Nantes, France

Aimen Bouchhima

TIMA Laboratory

Grenoble, France

Erik Brockmeyer

IMEC

Leuven, Belgium

Francky Catthoor

IMEC

Leuven, Belgium

and

Katholiek University

Leuven, Belgium

Wander Cesario

TIMA Laboratory

Grenoble, France

Yuen Hui Chee

University of California–Berkeley

Berkeley, California

Lawrence T. Clark

Arizona State University

Tempe, Arizona

Fabien Coelho

Ecole des Mines

Paris, France

Stefan Cserveny

CSEM

Neuchâtel, Switzerland

Raphaël David

ENSSAT/University of Rennes

Lannion, France

Vivek De

Intel Labs

Santa Clara, California

Peter Dytrych

Philips Digital Systems Laboratories

Leuven, Belgium

Laurent Fesquet

TIMA Laboratory

Grenoble, France

Joao Fragoso

TIMA Laboratory

Grenoble, France

Simone Gambini

Universita di Pisa

Pisa, Italy

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Lovic Gauthier

FLEETS

Fukuoka, Japan

Catherine H. Gebotys

University of Waterloo

Waterloo, Ontario, Canada

Cedric Ghez

IMEC

Leuven, Belgium

Gert Goossens

Target Compilers Technologies

Leuven, Belgium

Koji Inoue

Fukuoka University

Fukuoka, Japan

Ahmed A. Jerraya

TIMA Laboratory

Grenoble, France

Pradeep K. Khosla

Carnegie Mellon University

Pittsburgh, Pennsylvania

Ulrich Kremer

Rutgers University

Piscataway, New Jersey

Chidamber Kulkarni

University of California–Berkeley

Berkeley, California

Dirk Lanneer

Philips Digital Systems Laboratories

Leuven, Belgium

Dake Liu

Department of Electrical Engineering

Linköping University

Linköping, Sweden

Richard Lu

University of California–Berkeley

Berkeley, California

Alberto Macii

Politecnico di Torino

Torino, Italy

Morteza Maleki

University of Southern California

Los Angeles, California

Diana Marculescu

Carnegi Mellon University

Pittsburgh, Pennsylvania

Radu Marculescu

Carnegie Mellon University

Pittsburgh, Pennsylvania

Jean-Marc Masgonty

CSEM

Neuchâtel, Switzerland

Tycho van Meeuwen

IMEC

Leuven, Belgium

Giovanni de Micheli

Stanford University

Stanford, California

Miguel Miranda

IMEC

Leuven, Belgium

Vasily G. Moshnyaga

Fukuoka University

Fukuoka, Japan

Thierry J.-F. Omnès

Philips Semiconductors

Eindhoven, The Netherlands

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xi

Brian P. Otis

University of California–Berkeley

Berkeley, California

Massoud Pedram

University of Southern California

Los Angeles, California

Pierre-David Pfister

CSEM

Neuchâtel, Switzerland

Christian Piguet

CSEM & LAP-EPFL

Neuchâtel, Switzerland

Sébastien Pillement

ENSSAT/University of Rennes

Lannion, France

Nathan M. Pletcher

University of California–Berkeley

Berkeley, California

Jan M. Rabaey

University of California–Berkeley

Berkeley, California

Flavio Rampogna

CSEM

Neuchâtel, Switzerland

Marc Renaudin

TIMA Laboratory

Grenoble, France

Mohammed Es Sahliene

TIMA Laboratory

Grenoble, France

Olivier Sentieys

ENSSAT/University of Rennes

Lannion, France

Kamel Slimani

TIMA Laboratory

Grenoble, France

Phillip Stanley-Marbell

Carnegie Mellon University

Pittsburgh, Pennsylvania

Philip Strenski

IBM Watson Research Center

Yorktown Heights, New York

Eric Tell

Linköping University

Linköping, Sweden

Ingrid Verbauwhede

University of California–Los Angeles

Los Angeles, California

Patrick Volet

CSEM

Neuchâtel, Switzerland

Terry Tao Ye

Stanford University

Stanford, California

Sungjoo Yoo

TIMA Laboratory

Grenoble, France

Victor Zyuban

IBM Watson Research Center

Yorktown Heights, New York

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I-1

I

Low-Power Processors

and Memories

1 Techniques for Power and Process Variation Minimization..........................................1-1

Lawrence T. Clark and Vivek De

2 Low-Power DSPs................................................................................................................2-1

Ingrid Verbauwhede

3 Energy-Efficient Reconfigurable Processors....................................................................3-1

Raphaël David, Sébastien Pillement, and Olivier Sentieys

4 Macgic, a Low-Power Reconfigurable DSP......................................................................4-1

Flavio Rampogna, Pierre-David Pfister, Claude Arm, Patrick Volet,

Jean-Marc Masgonty, and Christian Piguet

5 Low-Power Asynchronous Processors .............................................................................5-1

Kamel Slimani, Joao Fragoso, Mohammed Es Sahliene, Laurent Fesquet,

and Marc Renaudin

6 Low-Power Baseband Processors for Communications.................................................6-1

Dake Liu and Eric Tell

7 Stand-By Power Reduction for SRAM Memories ...........................................................7-1

Stefan Cserveny, Jean-Marc Masgonty, and Christian Piguet

8 Low-Power Cache Design..................................................................................................8-1

Vasily G. Moshnyaga and Koji Inoue

9 Memory Organization for Low-Energy Embedded Systems .........................................9-1

Alberto Macii

6700_book.fm Page 1 Friday, July 1, 2005 10:02 AM

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