Digital logic and microprocessor design with VHDL

SAC 11 K E M T 1 I E O D lA C D D A T

Enoch 0. Hwang

Digital Logic and

Microprocessor Design

with VHDL

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Enoch O. Hwang

La Sierra University

Riverside

T H O M S O N

Canada Mexico Singapore Spain United Kingdom United States

T I H O I V I S O I M

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To my wife and children, Windy, Jonathan, f//7í/ Michelle

Contents

Preface xv

About the Author xix

• • # ##••••••••«*•

1 Designing Microprocessors 1

1.1 Overview of a Microprocessor 3

1.2 Design Abstraction Levels 5

1.3 Examples of a 2-to-1 Multiplexer 7

1.3.1 Behavioral Level 7

1.3.2 Gate Level 8

1.3.3 Transistor Level 10

1.4 Introduction to VHDL 10

1.5 Synthesis 13

1.6 Going Forward 14

1.7 Summary Checklist 14

1.8 Problems 16

• • • • • • •

2 Digital Circuits 17

2.1 Binary Numbers 18

2.2 Binary Switch 22

2.3 Basic Logic Operators and Logic Expressions 23

2.4 Truth Tables 24

2.5 Boolean Algebra and Boolean Functions 25

2.5.1 Boolean Algebra 25

'2.5.2 Duality Principle 28

2.5.3 Boolean Functions and their Inverses 29

v

2.6 Minterr-;.- u ■ Maxterms 33

2.6.1 Mint pi ms 33

* 2.6.2 Maxtor ms 36

2.7 Canonical, Standard, and Non-Standard Forms 38

2.8 Logic Gates and Circuit Diagrams 39

2.9 Designing a Car Security System 43

2.10 VHDL for Digital Circuits 45

2.10.1 VHDL Code for a 2-Input NAND Gate 46

2.10.2 VHDL Code for a 3-Input NOR Gate 47

2.10.3 VHDL Code for a Function 48

2.11 Summary Checklist 49

2.12 Problems 50

3 Combinational Circuits 54

3.1 Analysis of Combinational Circuits 55

3.1.1 Using a Truth Table 56

3.1.2 Using a Boolean Function 59

3.2 Synthesis of Combinational Circuits 60

’ 3.3 Technology Mapping 63

3.4 Minimization of Combinational Circuits 67

3.4.1 Karnaugh Maps 67

3.4.2 Don't-Cares 74

’ 3.4.3 Tabulation Method 75

' 3.5 Timing Hazards and Glitches 77

3.5.1 Using Glitches 79

3.6 BCD to 7-Segment Decoder 80

3.7 VHDL tor Combinational Circuits 82

3.7.1 Structural BCD to 7-Segment Decoder 83

3.7.2 Dataflow BCD to 7-Segment Decoder 88

3.7.3 Behavioral BCD to 7-Segment Decoder 89

3.8 Summaiy CheckIist 91

3.9 Problems 92

• ••#«** 1 ‘ * ..........

4 Standard Combinational Components 98

4.1 Signal Naming Conventions 99

4.2 Adder 100

4.2.1 Full Adder 100

4.2.2 Ripple-Carry Adder 101

'4.2.3 Carry Lookahead Adder 102

Contents

4.3 Two's Complement Binary Numbers 105

4.4 Subtractor 108

4.5 Adder-Subtractor Combination 109

4.6 Arithmetic Logic Unit 114

4.7 Decoder 117

4.8 Encoder 12 2

*4.8.1 Priority Encoder 123

4.9 Multiplexer 124

‘4.9.1 Using Multiplexers to Implement a Function 128

4.10 Tri-State Buffer 128

4.11 Comparator 130

4.12 Shifter 134

*4.12.1 Barrel Shifter 135

•4.13 Multiplier 136

4.14 Summary Checklist 139

4.15 Problems 139

f # • ••••••••••*•*

5 Implementation Technologies 145

5.1 Physical Abstraction 146

5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 147

5.3 CMOS Logic 148

5.4 CMOS Circuits 150

5.4.1 CMOS Inverter 151

5.4.2 CMOS NAND Gate 152

5.4.3 CMOS AND Gate 154

5.4.4 CMOS NOR and OR Gates 155

5.4.5 Transmission Gate 155

5.4.6 2-Input Multiplexer CMOS Circuit 156

5.4.7 CMOS XOR and XNOR Gates 158

5.5 Analysis of CMOS Circuits 159

'5.6 Using ROMs to Implement a Function 161

'5.7 Using PLAs to Implement a Function 164

5.8 Using PALs to Implement a Function 168

'5.9 Complex Programmable Logic Device (CPLD) 170

'5.10 Field Programmable Gate Array (FPGA) 173

5.11 Summary Checklist 175

5.12 Problems 175