Điện tử số - Phần 1 pdf

5/1

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

Course contents

• Digital design

• Combinatorial circuits: without status

• Sequential circuits: with status

• FSMD design: hardwired processors

Language based HW design: VHDL

5/2

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

Language based HW design:

a VHDL primer

• Introduction

• A first look at VHDL

• Signals and data types

• VHDL operators

• Concurrent versus sequential

statements

• Sequential construction statements

• Higher performance, less portability:

e.g. synthesis issues for Xilinx

5/3

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

Language based HW design:

a VHDL primer

Introduction

• A first look at VHDL

• Signals and data types

• VHDL operators

• Concurrent versus sequential

statements

• Sequential construction statements

• Higher performance, less portability:

e.g. synthesis issues for Xilinx

5/4

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Acronym:

 VHDL = VHSIC Hardware Description Language

 VHSIC = Very High Speed Integrated Circuit

• What is VHDL?

 A programming language for describing the behavior

of digital systems

 Design entry language, used for

Unambiguous specification at behavioral and RTL

level

Simulation (executable specification…)

Synthesis

Documentation

• Standardisation: IEEE 1076

 First version: 1986

 Second version: 1993

 New version about to appear

5/5

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• When to use VHDL instead of

schematics?

 Drawbacks:

VHDL is easy to learn but hard to master

(semantics are quite different from software

languages)

VHDL has a difficult syntax (Language sensitive

editors with templates for all language

constructs)

VHDL is very ‘wordy’: lots of code to type for just

a few simple things

A list of instructions is less intuitive to

understand than a block diagram for a human

being

VHDL is designed to make simulation efficient:

contains aspects that have hardly anything to do

with hardware behavior, but is useful to speed-up

event driven simulation

5/6

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• When to use VHDL instead of schematics?

 Easier to capture complex circuits: higher level

of abstraction with automated synthesis

you specify ‘add’ instead of jotting

down a specific type of adder: the

synthesis tool will instantiate the best

type of adder under timing, area &

power constraints

easy to parametrise (e.g. word length,

queue depth)

easy to specify arrays of components

 Portable across many tools for simulation,

synthesis, analysis, verification, … of different

vendors (e.g. Synopsys, Mentor Graphics, …)

5/7

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Limitations of VHDL

 The standard only describes syntax and

semantics, but not the coding style

you can specify the same behavior (e.g. MUX) in

an almost unlimited number of ways

each leading to a completely different

implementation (e.g. Multiplexor or tri-state bus)

which is synthesis tool dependent.

You should do lots of experimentation with style￾tool combinations to be able to predict how the

hardware will look like that will be synthesised. Is

prediction necessary? You also do not predict the

ASM generated by C; C is less efficient than ASM

but faster to write. Currently, it is hard to tolerate

the inefficiency caused by the higher level

specification for hardware.

Note: for DSP processors programmed in C, we do

predict ASM and have to experiment with style￾compiler combinations for efficiency reasons!!

5/8

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Limitations of VHDL (ctud)

 Only a subset of VHDL can be automatically

synthesised; each vendor supports a different

subset

 Only digital; special extension (not yet widely

adopted) for analog: VHDL-AMS (acronym for

VHDL Analog and Mixed Signal)

IEEE standard 1076.1-1999

is a super-set of the full IEEE VHDL

1076-1993 standard for digital design

5/9

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Abstraction levels

 Behavioral

Interconnected functions

Only info on functions or algorithms

(what)

Only timing needed to let the

function work correctly

OK for VHDL

Behavioral synthesisers immature;

used for high level executable

specification in top-down design and

manual synthesis into RTL

5/10

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Abstraction levels

 RTL

Interconnected registers and combinatorial units

Info on function (what) and architecture (how)

Cycle accurate

No technology dependent timing info

OK for VHDL

Good synthesisers

 Gate level

Interconnected gates and flip-flops

Info on function and architecture

Info on technology dependent timing (gate delays)

 Layout

Info on layout on silicon

Continuous timing

Analog effects

5/11

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Other hardware description languages

(HDL)

 Verilog

More widespread in USA than in

Europe

Often required for gate level or RTL

level ASIC sign-off

Never ending discussion which is

better

 PLD languages like ABEL, PALASM, …

These are more at the gate level,

capturing also technology dependent

features (e.g. detailed timing)

5/12

©

R.Lauwereins

Imec 2001

Digital

design

Combina￾torial

circuits

Sequential

circuits

FSMD

design

VHDL

VHDL primer: Introduction

• Difference between HDLs and traditional

software programming languages

 Concurrency: all hardware components operate

in parallel

 Data types: support is needed for arbitrary size

integers, bit vectors, fixed point numbers

 Concept of time