Compact Summary of VHDL phần 1 doc

|Summary |Design Units |Sequential Statements |Concurrent Statements |Predefined Types |Declarations |

|Resolution and Signatures |Reserved Words |Operators |Predefined Attributes |Standard Packages |

Version 1.4, please report any issues to [email protected]

Compact Summary of VHDL

This is not intended as a tutorial. This is a quick reference

guide to find the statement or statement syntax you need

to write VHDL code.

VHDL is case insensitive, upper case letters are equivalent to

lower case letters. Reserved words are in lower case by

convention and shown in bold in this document.

Identifiers are simple names starting with a letter and may

have letters and digits. The underscore character is allowed but

not as the first or last character of an identifier.

A comment starts with minus minus, "--", and continues to

the end of the line.

Indentation is used for human readability. The language is free

form with the characters space, tab and new-line being "white space."

Contents

● Design units

● Sequential Statements

● Concurrent Statements

● Predefined Types

● Declaration Statements

● Resolution and Signatures

● Reserved Words

● Operators

● Predefined Attributes

● VHDL standard packages and types

● Other Links

Notation used in this Compact Summary

Each item has:

a very brief explanation of possible use.

a representative, possibly not complete, syntax schema

one or more samples of actual VHDL code.

Compact Summary of VHDL

http://www.csee.umbc.edu/help/VHDL/summary.html (1 of 2) [22/12/2001 15:23:33]