Communication Architectures for Systems-on-Chip

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C M Y CM MY CY CMY K

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COMMUNICATION ARCHITECTURES FOR SYSTEMS-ON-CHIP COMMUNICATION ARCHITECTURES FOR SYSTEMS-ON-CHIP

Ayala

ISBN: 978-1-4398-4170-9

9 781439 841709

90000

COMMUNICATION ARCHITECTURES FOR

SYSTEMS-ON-CHIP

K11940

COMPUTER ENGINEERING

A presentation of state-of-the-art approaches from an industrial

applications perspective, Communication Architectures for Systems￾on-Chip shows professionals, researchers, and students how to

attack the problem of data communication in the manufacture of

SoC architectures.

With its lucid illustration of current trends and research improving

the performance, quality, and reliability of transactions, this is

an essential reference for anyone dealing with communication

mechanisms for embedded systems, systems-on-chip, and multi￾processor architectures—or trying to overcome existing limitations.

Exploring architectures currently implemented in manufactured

SoCs—and those being proposed—this book analyzes a wide range

of applications, including

• Well-established communication buses

• Less common networks-on-chip

• Modern technologies that include the use of carbon nanotubes

(CNTs)

• Optical links used to speed up data transfer and boost both

security and quality of service (QoS)

The book’s contributors pay special attention to newer problems,

including how to protect transactions of critical on-chip information

(personal data, security keys, etc.) from an external attack. They

examine mechanisms, revise communication protocols involved,

and analyze overall impact on system performance.

COMMUNICATION

ARCHITECTURES FOR

SYSTEMS-ON-CHIP

Embedded Systems

Series Editor

Richard Zurawski

SA Corporation, San Francisco, California, USA

Communication Architectures for Systems-on-Chip, edited by José L. Ayala

Real Time Embedded Systems Design and Analysis with Open-Source Operating

Systems, Ivan Cibrario Bertolotti and Gabriele Manduchi

Time-Triggered Communication, edited by Roman Obermaisser

CRC Press is an imprint of the

Taylor & Francis Group, an informa business

Boca Raton London New York

COMMUNICATION

ARCHITECTURES FOR

SYSTEMS-ON-CHIP

Edited by

José L. Ayala

CRC Press

Taylor & Francis Group

6000 Broken Sound Parkway NW, Suite 300

Boca Raton, FL 33487-2742

© 2011 by Taylor & Francis Group, LLC

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Version Date: 20111012

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Dedicado a quien me ense˜na cada d´ıa,

a quien me hace pensar,

a quien me sonr´ıe y me apoya,

a quien me estimula y causa admiraci´on.

Dedicado a ti.

This page intentionally left blank

Contents

List of Figures xv

List of Tables xxiii

Preface xxv

Acknowledgments xxvii

Author xxix

1 Introduction 1

Jos´e L. Ayala

1.1 Today’s Market for Systems-on-Chip . . . . . . . . . . . . . 1

1.2 Basics of the System-on-Chip Design . . . . . . . . . . . . . 3

1.2.1 Main Characteristics of the Design Flow . . . . . . . . 4

1.2.1.1 Interoperability . . . . . . . . . . . . . . . . 4

1.2.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.3 Power Consumption . . . . . . . . . . . . . . . . . . . 5

1.2.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2.5 Limitations of the Current Engineering Practices for

System-on-Chip Design . . . . . . . . . . . . . . . . . 7

1.3 Open Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Communication Buses for SoC Architectures 15

Pablo Garc´ıa del Valle and Jos´e L. Ayala

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1.1 Current Research Trends . . . . . . . . . . . . . . . . 17

2.1.2 Modeling and Exploring the Design Space of On-Chip

Communication . . . . . . . . . . . . . . . . . . . . . . 18

2.1.3 Automatic Synthesis of Communication Architectures 18

2.2 The AMBA Interface . . . . . . . . . . . . . . . . . . . . . . 19

2.2.1 AMBA 4 AXI Interface: AXI4 . . . . . . . . . . . . . 21

2.2.1.1 AXI4-Lite . . . . . . . . . . . . . . . . . . . . 22

2.2.1.2 AXI4-Stream . . . . . . . . . . . . . . . . . . 22

2.2.2 AMBA 3 AHB Interface . . . . . . . . . . . . . . . . . 22

vii

viii Contents

2.2.2.1 AMBA 3 AHB-Lite . . . . . . . . . . . . . . 24

2.2.2.2 Multilayer AHB Interface . . . . . . . . . . . 25

2.2.3 AMBA 3 APB Interface . . . . . . . . . . . . . . . . . 26

2.2.4 AMBA 3 ATB Interface . . . . . . . . . . . . . . . . . 27

2.2.5 AMBA Tools . . . . . . . . . . . . . . . . . . . . . . . 28

2.2.5.1 ARM’s CoreLink . . . . . . . . . . . . . . . . 28

2.2.5.2 ARM’s CoreSight . . . . . . . . . . . . . . . 30

2.2.5.3 Third-Party Tools . . . . . . . . . . . . . . . 30

2.3 Sonics SMART Interconnects . . . . . . . . . . . . . . . . . . 30

2.3.1 SNAP: Sonics Network for AMBA Protocol . . . . . . 32

2.3.2 SonicsSX Interconnect . . . . . . . . . . . . . . . . . . 33

2.3.3 SonicsLX Interconnect . . . . . . . . . . . . . . . . . . 33

2.3.4 SonicsMX Interconnect . . . . . . . . . . . . . . . . . 34

2.3.5 S3220 Interconnect . . . . . . . . . . . . . . . . . . . . 34

2.3.6 Sonics Tools . . . . . . . . . . . . . . . . . . . . . . . . 36

2.3.6.1 SonicsStudio . . . . . . . . . . . . . . . . . . 36

2.3.6.2 SNAP Capture Tool . . . . . . . . . . . . . . 38

2.4 CoreConnect Bus . . . . . . . . . . . . . . . . . . . . . . . . 38

2.4.1 Processor Local Bus (PLB) . . . . . . . . . . . . . . . 42

2.4.1.1 PLB6 . . . . . . . . . . . . . . . . . . . . . . 42

2.4.2 On-Chip Peripheral Bus (OPB) . . . . . . . . . . . . . 43

2.4.3 Device Control Register Bus (DCR) . . . . . . . . . . 43

2.4.4 Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.4.4.1 PLB-OPB Bridges . . . . . . . . . . . . . . . 44

2.4.4.2 AHB Bridges . . . . . . . . . . . . . . . . . . 44

2.4.5 Coreconnect Tools . . . . . . . . . . . . . . . . . . . . 45

2.4.5.1 Design Toolkits . . . . . . . . . . . . . . . . 45

2.4.5.2 PLB Verification: PureSpec . . . . . . . . . . 46

2.5 STBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.5.1 STBus Verification Tools . . . . . . . . . . . . . . . . 49

2.5.2 Towards NoC . . . . . . . . . . . . . . . . . . . . . . . 50

2.6 FPGA On-Chip Buses . . . . . . . . . . . . . . . . . . . . . . 50

2.6.1 Altera: Avalon . . . . . . . . . . . . . . . . . . . . . . 51

2.6.2 Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.6.2.1 IBM’s CoreConnect . . . . . . . . . . . . . . 51

2.6.2.2 Extensible Processing Platform . . . . . . . . 52

2.7 Open Standards . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.7.1 Introducing the OCP-IP . . . . . . . . . . . . . . . . . 55

2.7.2 Specification . . . . . . . . . . . . . . . . . . . . . . . 56

2.7.3 Custom Cores . . . . . . . . . . . . . . . . . . . . . . . 58

2.7.4 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.7.4.1 CoreCreator . . . . . . . . . . . . . . . . . . 60

2.7.4.2 OCP SystemC TLM Kit . . . . . . . . . . . 62

2.7.4.3 OCP Conductor . . . . . . . . . . . . . . . . 62

2.8 Wishbone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Contents ix

2.8.1 The Wishbone Bus Transactions . . . . . . . . . . . . 64

2.9 Other Specific Buses . . . . . . . . . . . . . . . . . . . . . . . 64

2.9.1 Automotive . . . . . . . . . . . . . . . . . . . . . . . . 65

2.9.2 Avionics . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.9.2.1 Military . . . . . . . . . . . . . . . . . . . . . 68

2.9.2.2 Civil . . . . . . . . . . . . . . . . . . . . . . . 68

2.9.2.3 Debugging in Avionics . . . . . . . . . . . . . 70

2.9.3 Home Automation . . . . . . . . . . . . . . . . . . . . 70

2.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.11 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2.12 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2.13 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3 NoC Architectures 83

Martino Ruggiero

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.2 Advantages of the NoC Paradigm . . . . . . . . . . . . . . . 85

3.3 Challenges of the NoC Paradigm . . . . . . . . . . . . . . . . 87

3.4 Principles of NoC Architecture . . . . . . . . . . . . . . . . . 88

3.4.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.4.2 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.4.2.1 Oblivious Routing Algorithms . . . . . . . . 94

3.4.2.2 Deterministic Routing Algorithms . . . . . . 97

3.4.2.3 Adaptive Routing Algorithms . . . . . . . . 99

3.4.2.4 Problems on Routing . . . . . . . . . . . . . 101

3.4.3 Flow Control . . . . . . . . . . . . . . . . . . . . . . . 101

3.4.3.1 Message-Based . . . . . . . . . . . . . . . . . 102

3.4.3.2 Packet-Based . . . . . . . . . . . . . . . . . . 103

3.4.3.3 Flit-Based . . . . . . . . . . . . . . . . . . . 103

3.5 Basic Building Blocks of a NoC . . . . . . . . . . . . . . . . 104

3.5.1 Router . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.5.1.1 Virtual Channels . . . . . . . . . . . . . . . . 105

3.5.2 Network Interface . . . . . . . . . . . . . . . . . . . . 105

3.5.3 Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.6 Available NoC Implementations and Solutions . . . . . . . . 106

3.6.1 IBM Cell . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.6.1.1 Element Interconnect Bus . . . . . . . . . . . 107

3.6.2 Intel TeraFLOPS . . . . . . . . . . . . . . . . . . . . . 108

3.6.2.1 TeraFLOPS Network . . . . . . . . . . . . . 109

3.6.3 RAW Processor . . . . . . . . . . . . . . . . . . . . . . 109

3.6.4 Tilera Architectures . . . . . . . . . . . . . . . . . . . 110

3.6.4.1 iMesh . . . . . . . . . . . . . . . . . . . . . . 112

3.6.5 Intel Single-Chip Cloud Computer . . . . . . . . . . . 112

3.6.6 ST Microelectronics STNoC . . . . . . . . . . . . . . . 114

3.6.7 Xpipes . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

x Contents

3.6.8 Aethereal . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.6.9 SPIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.6.10 MANGO . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.6.11 Proteo . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.6.12 XGFT . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

3.6.13 Other NoCs . . . . . . . . . . . . . . . . . . . . . . . . 120

3.6.13.1 Nostrum . . . . . . . . . . . . . . . . . . . . 121

3.6.13.2 QNoC . . . . . . . . . . . . . . . . . . . . . . 121

3.6.13.3 Chain . . . . . . . . . . . . . . . . . . . . . . 121

3.7 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.8 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4 Quality-of-Service in NoCs 127

Federico Angiolini and Srinivasan Murali

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.2 Architectures for QoS . . . . . . . . . . . . . . . . . . . . . . 129

4.2.1 Traffic Class Segregation in Space . . . . . . . . . . . 132

4.2.2 Traffic Class Segregation in Time . . . . . . . . . . . . 134

4.2.3 Other Methods for Traffic Class Segregation . . . . . . 137

4.2.4 Fairness of Traffic Delivery . . . . . . . . . . . . . . . 138

4.2.5 Monitoring and Feedback . . . . . . . . . . . . . . . . 139

4.2.6 Memory Controllers . . . . . . . . . . . . . . . . . . . 139

4.2.7 Methods for QoS Analysis . . . . . . . . . . . . . . . . 140

4.2.7.1 Worst-Case Analysis . . . . . . . . . . . . . . 141

4.2.7.2 Average-Case Analysis . . . . . . . . . . . . 146

4.2.8 Synthesis Methods for Supporting QoS . . . . . . . . . 147

4.2.9 Meeting Average-Case Constraints . . . . . . . . . . . 147

4.2.9.1 Meeting Worst-Case QoS Constraints . . . . 149

4.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.4 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

5 Emerging Interconnect Technologies 159

Davide Sacchetto, Mohamed Haykel Ben-Jamaa, Bobba Shashi

Kanth, and Fengda Sun

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

5.1.1 Traditional Interconnects . . . . . . . . . . . . . . . . 161

5.1.2 General Organization of the Chapter . . . . . . . . . . 162

5.2 Optical Interconnects . . . . . . . . . . . . . . . . . . . . . . 162

5.3 Plasmonic Interconnects . . . . . . . . . . . . . . . . . . . . . 165

5.4 Silicon Nanowires . . . . . . . . . . . . . . . . . . . . . . . . 167

5.4.1 Bottom-Up Techniques . . . . . . . . . . . . . . . . . . 168

5.4.1.1 Vapor-Liquid-Solid Growth . . . . . . . . . . 168

5.4.1.2 Laser-Assisted Catalytic Growth . . . . . . . 168

5.4.1.3 Chemical Vapor Deposition . . . . . . . . . . 169

Contents xi

5.4.1.4 Opportunities and Challenges of Bottom-Up

Approaches . . . . . . . . . . . . . . . . . . . 169

5.4.2 Top-Down Techniques . . . . . . . . . . . . . . . . . . 170

5.4.2.1 Standard Photolithography Techniques . . . 170

5.4.2.2 Miscellaneous Mask-Based Techniques . . . . 173

5.4.2.3 Spacer Techniques . . . . . . . . . . . . . . . 174

5.4.2.4 Nanomold-Based Techniques . . . . . . . . . 174

5.4.2.5 Opportunities and Challenges of Top-Down

Approaches . . . . . . . . . . . . . . . . . . . 175

5.4.3 Focus on the Spacer Technique . . . . . . . . . . . . . 175

5.4.4 Focus on the DRIE Technique . . . . . . . . . . . . . 178

5.5 Carbon Nanotubes . . . . . . . . . . . . . . . . . . . . . . . . 181

5.5.1 Physics of Carbon Nanotubes . . . . . . . . . . . . . . 182

5.5.2 Types of CNTs for Various Interconnects . . . . . . . 183

5.5.3 Synthesis of CNT: A Technology Outlook . . . . . . . 185

5.6 3D Integration Technology . . . . . . . . . . . . . . . . . . . 186

5.6.1 Metal/Poly-Silicon TSVs . . . . . . . . . . . . . . . . 187

5.6.2 Carbon Nanotube TSVs . . . . . . . . . . . . . . . . . 187

5.6.3 Optical TSVs . . . . . . . . . . . . . . . . . . . . . . . 189

5.7 Summary and Conclusions . . . . . . . . . . . . . . . . . . . 190

5.8 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

5.9 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6 HeTERO: Hybrid Topology Exploration for RF-Based On￾Chip Networks 201

Soumya Eachempati, Reetuparna Das, Vijaykrishnan Narayanan,

Yuan Xie, Suman Datta, and Chita R Das

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.2 RF-Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . 204

6.3 State-of-Art Topologies . . . . . . . . . . . . . . . . . . . . . 207

6.3.1 Mesh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.3.2 Concentrated Mesh . . . . . . . . . . . . . . . . . . . . 207

6.3.3 Flattened Butterfly . . . . . . . . . . . . . . . . . . . . 208

6.3.4 Hierarchical Topology . . . . . . . . . . . . . . . . . . 209

6.3.5 Impact of Locality . . . . . . . . . . . . . . . . . . . . 212

6.4 RF-Topology Modeling . . . . . . . . . . . . . . . . . . . . . 214

6.5 RF-Based Topologies . . . . . . . . . . . . . . . . . . . . . . 216

6.6 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . 218

6.6.1 Technology Assumptions . . . . . . . . . . . . . . . . . 218

6.6.2 Simulation Setup . . . . . . . . . . . . . . . . . . . . . 219

6.7 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

6.7.1 Simple Mesh . . . . . . . . . . . . . . . . . . . . . . . 221

6.7.1.1 16 Nodes . . . . . . . . . . . . . . . . . . . . 221

6.7.1.2 36 Nodes . . . . . . . . . . . . . . . . . . . . 225

6.7.1.3 64 Nodes . . . . . . . . . . . . . . . . . . . . 225

xii Contents

6.7.1.4 256 nodes . . . . . . . . . . . . . . . . . . . . 229

6.7.2 Cmesh and Hierarchical Topologies . . . . . . . . . . . 234

6.7.2.1 CMESH . . . . . . . . . . . . . . . . . . . . . 234

6.7.2.2 Hierarchical Topology . . . . . . . . . . . . . 234

6.8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

6.9 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 241

6.10 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

6.11 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

6.12 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

7 Intra-/Inter-Chip Optical Communications 249

Braulio Garc´ıa-C´amara

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

7.2 Photonic Components for On-Chip Optical Interconnects . . 254

7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 254

7.2.2 Optical Sources . . . . . . . . . . . . . . . . . . . . . . 255

7.2.2.1 In-Chip Light Sources: Small Emitting

Devices . . . . . . . . . . . . . . . . . . . . . 255

7.2.2.2 Out-of-Chip Light Sources: Modulators . . . 266

7.2.3 Optical Channels . . . . . . . . . . . . . . . . . . . . . 276

7.2.3.1 In-Waveguide Configurations . . . . . . . . . 277

7.2.3.2 Free-Space Optical Interconnect (FSOI) . . . 283

7.2.4 Photodetectors . . . . . . . . . . . . . . . . . . . . . . 286

7.2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 295

7.3 Why Optical Links? Comparison of Electrical and Optical

Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

7.3.1 Power Consumption . . . . . . . . . . . . . . . . . . . 297

7.3.2 Propagation Delay . . . . . . . . . . . . . . . . . . . . 299

7.3.3 Bandwidth Density and Crosstalk Noise . . . . . . . . 300

7.3.4 Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . 302

7.4 Photonic Networks . . . . . . . . . . . . . . . . . . . . . . . . 305

7.5 New Optical Nanocircuits Based on Metamaterials . . . . . . 306

7.6 Present and Future of the Intra-/Inter-Chip Optical Interconnections

308

7.7 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

7.8 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

8 Security Issues in SoC Communication 323

Jos´e M. Moya, Juan-Mariano de Goyeneche, and Pedro Malag´on

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

8.1.1 Side-Channel Attacks . . . . . . . . . . . . . . . . . . 326

8.1.2 Sources of Information Leakage . . . . . . . . . . . . . 329

8.1.3 Overview of Countermeasures . . . . . . . . . . . . . . 332

8.2 Power Analysis Attacks . . . . . . . . . . . . . . . . . . . . . 333

8.2.1 Simple Power Analysis . . . . . . . . . . . . . . . . . . 333

Contents xiii

8.2.2 Differential Power Analysis Attacks . . . . . . . . . . . 336

8.2.3 Correlation Power Analysis . . . . . . . . . . . . . . . 338

8.2.4 Stochastic Methods . . . . . . . . . . . . . . . . . . . 339

8.2.5 Higher Order DPA . . . . . . . . . . . . . . . . . . . . 341

8.2.6 Attacks on Hiding . . . . . . . . . . . . . . . . . . . . 341

8.2.7 Attacks on Masking . . . . . . . . . . . . . . . . . . . 343

8.2.8 ECC-Specific Attacks . . . . . . . . . . . . . . . . . . 344

8.2.9 Power Analysis Attacks on Faulty Devices . . . . . . . 345

8.2.10 Multichannel Attacks . . . . . . . . . . . . . . . . . . 346

8.3 Logic-Level DPA-Aware Techniques . . . . . . . . . . . . . . 347

8.3.1 Dual-Rail Precharge Logic . . . . . . . . . . . . . . . . 348

8.3.1.1 Sense-Amplifier Based Logic . . . . . . . . . 349

8.3.1.2 Wave Dynamic Differential Logic . . . . . . . 349

8.3.1.3 Dual-Spacer Dual-Rail Precharge Logic . . . 354

8.3.1.4 Three-Phase Dual-Rail Precharge Logic . . . 355

8.3.2 Charge Recovery Logic . . . . . . . . . . . . . . . . . . 355

8.3.3 Masked Logic Styles . . . . . . . . . . . . . . . . . . . 357

8.3.3.1 Random Switching Logic . . . . . . . . . . . 360

8.3.3.2 Masked Dual-Rail Precharge Logic . . . . . . 361

8.3.3.3 Precharge Masked Reed-Muller Logic . . . . 367

8.3.4 Asynchronous Circuits . . . . . . . . . . . . . . . . . . 369

8.3.4.1 Path Swapping . . . . . . . . . . . . . . . . . 370

8.4 Architecture-Level DPA-Aware Techniques . . . . . . . . . . 370

8.4.1 Current Flattening . . . . . . . . . . . . . . . . . . . . 371

8.4.2 Double-Data-Rate Computation . . . . . . . . . . . . 372

8.4.3 Dynamic Reconfiguration . . . . . . . . . . . . . . . . 373

8.4.4 Stream-Oriented Reconfigurable Unit (SORU) . . . . 374

8.5 Algorithm-Level DPA-Aware Techniques . . . . . . . . . . . 377

8.5.1 Randomized Initial Point . . . . . . . . . . . . . . . . 378

8.5.2 Avoiding Cold Boot Attacks . . . . . . . . . . . . . . . 379

8.6 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

8.7 Traps and Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . 381

8.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

8.9 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

8.10 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Index 403

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