Advanced digital systems : experiments and concepts with CPLDS

Advanced Digital Systems:

Experiments and Concepts with CPLDs

Advanced Digital Systems:

Experiments and Concepts with CPLDs

by

Leo Chartrand

T H O I V I S O N

-------------^ -------------

I DELM AR LEARNING C a n a d a Me I U n i t e d K i n g d o m Un

THOIVISON

D E L fS A A R L E A R N I N G

AdvaDced Digital Systems: Eiperimeots and Concepts with CPLDs

Leo Chartrand

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Contents

Preface

Intended A u d ie n c e x ........................................................................................................................................................... ^

A bout This B o o k .................................................................................................................................................................

Student C D -R O M ............................................................................................................................................................... xi

Instructor's C D -R O M .......................................................................................................................................................... xi

H ow to Use This B o o k .....................................................................................................................................................xii

General Guidelines...........................................................................................................................................................

Specific Issues Regarding the First Half andSecond Half of the Book................................................................... xili

A ck n o w le d g m e n ts.............................................................................................................................................................xiv

A bo u t the A uthor...............................................................................................................................................................xlv

D e d ic a tio n ............................................................................................................................................................................xiv

Lab 1 Logic Gate Systems

Introductory Inform ation....................................................................................................................................................1

Decimal Number System ...................................................................................................................................................1

Binary Numbers................................................................................................................................................................... 2

Binary Numbers and Digital Systems..............................................................................................................................2

Switches, LEDs, and Digital Systems...............................................................................................................................i

The N O T Gate......................................................................................................................................................................€

The AND Gate...................................................................................................................................................................... 7

The OR Gate.........................................................................................................................................................................7

The Three-Input OR Gate................................................................................................................................................11

The NAND Gate and the NOR Gate.............................................................................................................................11

The XOR Gate and the XNOR Gate..............................................................................................................................12

Alternate Logic Gate Symbols...........................................................................................................................................1 •

Vending Machine System................................................................................................................................................l i

Altera UP Board.................................................................................................................................................................1 J

Older Generation I C s ...................................................................................................................................................... 21

PowerPoint Presentation...................................................................................................................................................22

Lab W ork Procedure...........................................................................................................................................................22

Design a Vending Machine System ..............................................................................................................................22

eomeni»

Lab Exercises and Questions................................................................................................................................... 45

Lab Exercises.............................................................................................................................................................45

Lab Questions.......................................................................................................................................................... 45

Conclusions..................................................................................................................................................................46

Lab 2 Older Generation Logic Gate Systems Versus CPLD Systems

Introductory Information.........................................................................................................................................47

VHDL Fundamentals................................................................................................................................................ 48

VHDL Selected Signal Assignment......................................................................................................................... 48

Comparing the Design Cycle of an Older Generation 1C System to a CPLD 1C System................................50

Converting an Old 1C Technology System to a CPLD 1C System......................................................................52

Old 1C Technology System Defined by a Truth Table......................................................................................... 53

PowerPoint Presentation.......................................................................................................................................... 58

Lab Work Procedure................................................................................................................................................. 58

VHDL Vending Machine System.............................................................................................................................58

Lab Exercises and Questions...................................................................................................................................65

Lab Exercises............................................................................................................................................................ 65

Lab Questions...........................................................................................................................................................67

Conclusions.............................................................................................................................................................. 67

Lab 3 Flip-Flops, Shift Registers, and Switch Bounce

Introductory Information........................................................................................................................................ 69

SR Flip-Flop Fundamentals.....................................................................................................................................69

D Flip-Flop Fundamentals...................................................................................................................................... 73

Shift Register Fundamentals.................................................................................................................................. 74

Switch Bounce.........................................................................................................................................................74

Switch Debounce System....................................................................................................................................... 76

VHDL Shift Register.................................................................................................................................................80

UP Board Pushbuttons............................................................................................................................................81

PowerPoint Presentation......................................................................................................................................... 81

Lab Work Procedure.................................................................................................................................................81

Build and Test a Switch Debounce System..........................................................................................................81

Lab Exercises and Questions.................................................................................................................................. 85

Lab Exercises............................................................................................................................................................86

Lab Questions......................................................................................................................................................... 90

Conclusions.................................................................................................................................................................93

Lab 4 Serial and Parallel Data Transfer Systems

Introductory Information..........................................................................................................................................

Flip-Flop Asynchronous Inputs........................................................................................................................ 95

Using Asynchronous Inputs to Load a Shift Register............................................................................... 95

Recirculating a Shift Register.................................................................................................................... 93

Serial Data Transfer System................................................................................................................................. 100

Latch Fundamentals..............................................................................................................................................100

Data Registers....................................................................................................................................................... 101

Parallel Data Transfer System...............................................................................................................................103

PowerPoint Presentation....................................................................................................................................... IO 3

Lab Work Procedure...............................................................................................................................................103

Design a Serial Data Transfer System..................................................................................................................103

Lab Exercises and Q uestions........................................................................................................................................

Lab Exercises...................................................................................................................................................................‘'0 ^

Lab Questions.................................................................................................................................................................

C o n c lu sio n s........................................................................................................................................................................^ ^ ^

Lab 5 |K Flip Flop and Counter Fundamentals

Introductory Inform ation..............................................................................................................................................

JK Flip-Flop Fundamentals........................................................................................................................................... 113

Counter Fundamentals.................................................................................................................................................

Down Counters............................................................................................................................................................. 11 ^

Asynchronous and Synchronous Presettable Counters..........................................................................................116

Combination Up/Down Counter............................................................................................................................... 11 7

Parallel Counters............................................................................................................................................................11 7

VHDL Binary Counter...................................................................................................................................................1 f 9

VHDL BCD Counter..................................................................................................................................................... 120

Frequency Division........................................................................................................................................................122

PowerPoint Presentation...............................................................................................................................................123

Lab W ork Procedure...................................................................................................................................................... 124

Design a Random Number Generator System........................................................................................................ 124

Lab Exercises and Q uestions.......................................................................................................................................126

Lab Exercises..................................................................................................................................................................126

Lab Questions................................................................................................................................................................1 31

C o n c lu sio n s....................................................................................................................................................................... 131

Lab 6 Digital Display Decoder System

Introductory Inform ation............................................................................................................................................. 133

Digital Displays.............................................................................................................................................................. 133

Basic Operation of a Seven-Segment Decoder.......................................................................................................1 34

Hexadecimal Numbers (HEX Num bers).................................................................................................................. 1 37

VHDL Seven-Segment Decoder..................................................................................................................................1 39

Pow erPoint Presentation...............................................................................................................................................141

Lab W ork Procedure...................................................................................................................................................... 141

Add a Digital Display to the Random Number Generator System of Lab 5 ....................................................141

Lab Exercises and Q uestions.......................................................................................................................................144

Lab Exercises..................................................................................................................................................................144

Lab Questions............................................................................................................................................................... 145

Conclusions................................................................................................................................................................... 145

Lab 7 "1 of X" Decoder and Encoder Systems

Introductory Inform ation.............................................................................................................................................14 7

"1 of X" Decoder Application: Camera Scanner....................................................................................................149

VHDL Decoder.............................................................................................................................................................. 149

"1 of X" Encoder.......................................................................................................................................................... 151

"1 of X" Encoder Application: SPST Keypad.......................................................................................................... 152

VHDL Encoder............................................................................................................................................................... 1 5 2

PowerPoint Presentation.............................................................................................................................................. I 54

Lab W ork Procedure.........................................................................................................................................................

Build and Test A Keypad Encoder System............................................................................................................... 15 4

Lab Exercises and Q uestions................................................................................................................................ I 55

viii ^UIILCMU

Lab Exercises..........................................................................................................................................................

Lab Questions........................................................................................................................................................

Conclusions...............................................................................................................................................................

Lab 8 Multiplexer and Demultiplexer Systems

Introductory Information......................................................................................................................................

The Multiplexer (MUX).........................................................................................................................................

AVH DL M UX........................................................................................................................................................

The Demultiplexer (DEMUX)...............................................................................................................................

AVH DL DEMUX...................................................................................................................................................

A MUX/DEMUX Security System......................................................................................................................... ^

Time Division Multiplexing...................................................................................................................................^

Using A MUX As A Logic Cate System................................................................................................................^

PowerPoint Presentation.......................................................................................................................................

Lab Work Procedure:............................................................................................................................................

Design a MUX/DEMUX Security System............................................................................................................^

Lab Exercises and Questions................................................................................................................................ ^75

Lab Exercises..........................................................................................................................................................^ 75

Lab Questions.......................................................................................................................................................

Conclusions...............................................................................................................................................................181

Lab 9 Matrix Keypad Encoder System

Introductory Information...................................................................................................................................... 183

Matrix Keypad Theory..........................................................................................................................................183

Matrix Keypad Encoder: Operation Summary...................................................................................................184

Matrix Keypad Encoder: Operational Details..................................................................................................... 185

PowerPoint Presentation....................................................................................................................................... 188

Lab Work Procedure.............................................................................................................................................. 188

Design a Matrix Keypad Encoder System.......................................................................................................... 188

MAX and FLEX 1C Considerations:.....................................................................................................................189

Lab Exercises and Questions................................................................................................................................189

Lab Exercises:........................................................................................................................................................ 189

Lab Questions.......................................................................................................................................................190

Conclusions:...........................................................................................................................................................190

Lab 10 Arithmetic Systems

Introductory Information......................................................................................................................................191

Binary Addition......................................................................................................................................................191

Fundamental Concepts for Subtraction: 2s Complement Notation............................................................... 192

Case 1: Design a 4-Bit Arithmetic System.........................................................................................................195

Case 2: Design an 8-Bit Arithmetic System........................................................................................................195

Addition Using 5-Bit 2CN Numbers and Arithmetic Overflow........................................................................ 196

Arithmetic Overflow Detection System..............................................................................................................199

Combination Adder / Subtractor System........................................................................................................... 199

2CN Special Case: The Largest Negative Number in the Valid Range.......................................................... 201

The Altera "LPM_ADD_SUB" Symbol................................................................................................................. 202

PowerPoint Presentation.......................................................................................................................................202

Lab Work Procedure.............................................................................................................................................. 202

Design a 4-Bit Adder/Subtractor System........................................................................................................... 202

Contents

Lab Exercises and Q uestions........................................................................................................................................ 2 0 3

Lab Exercises.................................................................................................................................................................2 0 3

Lab Questions.............................................................................................................................................................. 2 0 6

Conclusions.................................................................................................................................................................. 2 0 6

Lab 11 Memory System Fundamentals

Introductory Inform ation............................................................................................................................................ 20 9

Memory System Terminology................................................................................................................................... 20 9

RAM Architecture Fundamentals.............................................................................................................................. 212

Tri-State Buffer Theory................................................................................................................................................ 21 3

Tri-State Buffers and RAM ..........................................................................................................................................2 1 6

RAM Addressing...........................................................................................................................................................21 7

Separating the "Read" and "Write" Operations...................................................................................................218

Bidirectional I/O RAM Architecture.......................................................................................................................... 2 2 0

ROM Architecture Fundamentals.............................................................................................................................. 222

RAM and ROM Schematic Symbols......................................................................................................................... 223

ROM Light Sequencer System and Memory Map Diagram s.............................................................................224

PowerPoint Presentation..............................................................................................................................................2 2 6

Lab W ork Procedure..................................................................................................................................................... 2 2 6

Lab Work Procedure Part 1: Store Today's Date into an 834 RAM ...................................................................226

Lab Work Procedure Part 2; Design a ROM Light Sequencer............................................................................228

Lab Exercises and Q uestions......................................................................................................................................23 2

Lab Exercise.................................................................................................................................................................. 23 2

Lab Questions.............................................................................................................................................................. 235

Conclusions:.................................................................................................................................................................. 236

Lab 12 Liquid Crystal Displays (LCD)

Introductory Inform ation.............................................................................................................................................239

Seven-Segment LCD Construction D iagram ..........................................................................................................24 0

Seven-Segment LCD Decoder System..................................................................................................................... 242

Display Technology Evolution....................................................................................................................................242

Dot Matrix Displays (DM D) Using the HD44780 ControllenDMD Fundamentals...........................................243

DMD and Computer Communications...................................................................................................................24 6

Displaying Data on a D M D ........................................................................................................................................2 4 6

DMD CG RO M ...............................................................................................................................................................24 7

DMD D DRA M ...............................................................................................................................................................24 9

DMD C G R A M ...............................................................................................................................................................251

DMD Commands Summary...................................................................................................................................... 25 4

A ROM-Based Electronic Billboard System..............................................................................................................255

A ROM-Based Electronic Billboard System: System Communication................................................................ 25 6

Sample Program #1: Display a Two-Word Message.............................................................................................25 7

Sample Program #2: Display a "Happy Face" Custom Character......................................................................2 58

PowerPoint Presentation.............................................................................................................................................. 261

Lab W ork Procedure......................................................................................................................................................261

Build an Electronic Billboard System........................................................................................................................ 261

Lab Exercises and Q uestions...................................................................................................................................... 265

Lab Exercises............................................................................................................................................................. 265

Lab Questions............................................................................................................................................................. 267

C o n c lu sio n s........................................................................................................................................................... 268

Contents

A p p e n d ix A T h e E v o lu t io n o f R O M a n d R A M

Types of ROM; MROM, PROM. EPROM, EEPROM, and FLASH.......................................................................271

ROM Tim ing Diagram s..........................................................................................................................................275

Types of RAM; SRAM and D R A M ...................................................................................................................... 276

SRAM...................................................................................................................................................................... 276

DRAM.....................................................................................................................................................................276

DRAM Evolution...................................................................................................................................................... 280

Fast Page Mode (FPM) DRAM............................................................................................................................ 280

Extended Data Out (ED O )...................................................................................................................................281

Synchronous DRAM (SDRAM)............................................................................................................................ 281

Double Data Rate Synchronous DRAM (DDR SDRAM).................................................................................... 281

Direct Rambus DRAM (DRDRAM)........................................................................................................................281

Memory System D esign ....................................................................................................................................... 281

Data Bus Expansion Design: Combine 1634 ROMs to Make a 1638 ROM System..................................... 282

Address Bus Expansion Design: Combine 1634 ROMs to Make a 3234 ROM System............................... 284

System Memory Map Diagram (SMMD)........................................................................................................... 286

Data and Address Bus Expansion Design: Combine 3234 ROMs to Make a 6438 ROM System..............287

Q uestions..................................................................................................................................................................288

A p p e n d ix B V H D L D e s ig n G u id e

Correcting VH D L Syntax Errors..........................................................................................................................291

Making Changes to a Functional VH D L D esign............................................................................................ 293

A p p e n d ix C F L E X E x p a n s io n H e a d e r G u id e

FLEX Expansion Header Pin Number D ia gram ..............................................................................................295

Connecting a DM D to the FLEX Expansion Header..................................................................................... 296

A p p e n d ix D F o r m s a n d G u id e s f o r t h e D M D L a b 1 2 P r o je c t

DM D Com m and S um m ary.................................................................................................................................300

CCRO M /CGRAM T ab le ........................................................................................................................................ 301

DM D Programming Form (or Memory Map D iagram ).............................................................................. 302

DM D CCRAM Drawing G uide............................................................................................................................304

A p p e n d ix E S u m m a r y S h e e t f o r F L E X 1C D e s ig n s :

U s in g " L a b 1 " a s a G u id e ............................................................................................................................. 305

A p p e n d ix F A lt e r a S im u la t o r G u i d e .....................................................................................................309

I n d e x .............................................................................................................................................................................

Preface

Intended Audience

Advanced Digital Systems: Experiments and Concepts with CPLDs is a lab manual that is targeted at

any college or university that teaches digital principles. It is written at a level that can be easily

understood by first-year students. This book includes a set of 12 labs. The labs teach digital

fundamental concepts and apply these concepts to complex programmable logic devices

(CPLD) lab experiments using the Altera laboratory package. All labs include assignment

questions that can be completed outside of the lab and PowerPoint presentations that students

can use to review digital concepts. Many labs include design projects that will test a student's

ability to apply learned knowledge. Because this book includes an explanation of digital

concepts, it can stand on its own as a single source of information. A separate formal textbook

is not required to learn the digital principles.

Advanced Digital Systems: Experiments and Concepts with CPLDs can be used at a community

college with a 2-year technician program and a 3-year technology program. A 2-year program

typically needs "application approach" labs. A 3-year program typically needs "design

approach" labs. An "application approach" lab has students building and testing a system

studied in class, which has a predetermined response. A "design approach" lab has students

building the basic system and then using original thinking to improve or modify the system

operation.

To use this book as an "applications approach" lab book, students would build and test the

basic system included at the beginning of each lab exercise. The optional design work exercises

that follow the basic system can either be omitted or an instructor can provide and study the

solution for these design exercises with the students prior to the scheduled lab class. This

method essentially converts a "design" lab into an "application" lab. Thus, an instructor

controls the "design approach" or "application approach" by the amount of pre-lab solution

revealed in class prior to the lab.

To use this book as a "design approach" lab book, students would build and test the basic

system included at the beginning of each lab exercise and then follow that up with a selected

number of optional design exercises provided in the book. The final result is a book that can be

used to force original thinking (design approach), or solutions can be reviewed prior to the lab

to convert the lab into an application lab.

Many colleges or universities may find that this book can stand on its own as a single

source of digital information. Other colleges or universities that teach a more advanced or

intense course in digital principles can use this book in the lab and use a traditional textbook

for class work.

A CPLD design minimizes the amount of electrical wiring and eliminates the use of

complicated test equipment. As a result of this reduction in engineering complexity, it is

feasible for younger, less-experienced students to use this book.

xíí Preface

About This Book

To understand the value of this book you need to review the history of using digital integrated

circuits (ICs) or chips to teach digital fundamentals. Before the advent of the CPLDs, digital

fundamentals courses required students to have an electrical principles background. Digital

systems were pieced together with single-function transistor transistor logic (TTL) ICs. These

designs would often require five or six TTL ICs. The wiring would often be very complex and

messy. Digital test equipment would often be needed to make the system functional.

Another problem with TTLIC technology is obsolescence and sourcing laboratory packages.

TTL IC technology is over 30 years old and finding a source for replacement parts is more

difficult with each passing year. TTL IC technology laboratory packages (also called logic trainer

systems) are expensive to replace and difficult to maintain.

Using TTL IC technology prevents students from testing VHDL designs. VHDL is an acronym

for the VHSIC Hardware Description Language. VHSIC is an acronym for Very High Speed

Integrated Circuit. VHDL is a state-of-the-art hardware design language. Exposing students to this

industry-accepted standard is very beneficial. CPLD technology is needed to teach VHDL in a lab

environment.

Altera Corporation was founded in 1983. Altera is one of the world pioneer manufacturer of

CPLD ICs. The Altera University Program (UP) division was founded to offer schools a CPLD

design laboratory package. The package is called the UP board. Using a UP board to build and test

digital systems eliminates most of the wiring. A CPLD is a programmable device. Altera also

developed the MAX+PLUS® II development system. It is a fully integrated software package that

enables design entry, synthesis, verification, design simulation, and CPLD programming. It allows

Altera customers to quickly implement designs using CPLDs. A student edition comes with the

UP board. A student uses a PC and the MAX+PLUS® II software to draw a diagram of the digital

system and then transfers the entire system into one CPLD IC (programs the IC). A single CPLD

can easily accommodate a complex digital system design that would require hundreds of older

generation TTL ICs.

CPLD technology allows students to concentrate on digital principles and not the electrical

wiring. Reducing the wiring complexity also allows instructors to manage large lab group sizes.

Helping a student in the lab becomes an exercise in reviewing a digital system diagram as

opposed to analyzing messy project boards with four to five ICs with 50 or 60 wires.

The Altera UP board is very affordable ($149 US) compared to TTL-style digital logic trainers

costing thousands of dollars. A school can equip an entire 20-station UP board lab at nearly the

same cost as a single TTL IC technology laboratory package. Some schools choose to have

students purchase their own personal UP board.

Many digital concepts books currently on the market present concepts quickly and all at the

same time. Students are shown the entire forest before they get to look at a single tree. Some

students find this approach confusing and demoralizing. This book presents concepts

incrementally. Students are not asked to digest all the digital principles at once. Care has been

taken to ensure students progress systematically from one digital concept to the next. This

approach creates a positive class atmosphere because students are confident.

Student CD-ROM

This book includes a CD-ROM with the MAX+PLUS® II software, PowerPoint presentations and

the VHDL code for various labs. The students can use the PowerPoint presentations to review

digital concepts.

Instructor's CD-ROM

An instructor's CD-ROM is available and it includes many resources;

• The solutions to all lab exercises and lab questions.

• The Altera UP board user guides.

Preface xiii

An instructor's guide that explains how to set up and protect the Altera UP board from

damage in the lab.

Suggestions and guides for lab and classroom activity.

Tutorial questions. The problem sets can be used in class as a tutorial or they can be

handed out as homework assignment questions.

Solutions to tutorial questions.

A copy of Appendix E. Appendix E is a summary sheet for FLEX IC designs. It

summarizes how to use "Lab 1 as a guide." Extra copies can be printed and left at each

station in the lab.

Lecture note transparencies.

A discrete IC (TTL IC) lab and lab solution. This lab is optional and it can be used to

supplement the CPLD labs.

PowerPoint presentations.

How TO Use This Book

General Guidelines

Each lab contains a list of Equipment, Objectives, Introductory Information, PowerPoint

Presentation, Lab Work Procedure, Lab Exercises and Questions, and Conclusions. Most digital

fundamental courses are typically scheduled with weekly lecture classes and a weekly lab. An

instructor can use the weekly lecture classes to present the material found in the objectives,

introductory information, and the PowerPoint presentation. The instructor also can use the

weekly lecture class to present and review the Instructor's CD-ROM tutorial questions. This will

prepare the students for the weekly lab class and allow them to start immediately at the lab work

procedure section of the book when they enter the lab. The instructor can control the complexity

of the lab activity. Each lab includes a set of lab exercises that instructors can optionally pick and

choose from. Instructors can make a lab more complex by assigning more lab exercises, or they

can make it less complicated by reducing the number of lab exercises. Many labs include exercises

that can be used as lab projects. Instructors also can control the challenge level by picking and

choosing from the various project suggestions. Each lab includes lab questions. These questions

are problem sets that can be assigned to students and completed as a homework assignment.

Specific Issues Regarding the First Haif and

Second Half of the Book

The first half of the book includes Labs 1 to 5. These labs introduce students to basic logic gate

theory, shift registers, data registers, and counters. The first five labs of this book are an

abbreviation of the material presented in my first book Digital Fundamentals: Experiments and

Concepts with CPLDs, ISBN: 1401842461, which was published in the fall of 2003. My first book

covers the topics presented in Labs 1 to 5 at a slower pace using a series of 16 labs and 4 projects.

The second half of the book includes Labs 6 to 12. These labs take the building blocks

presented in the first five labs and apply them to advanced systems using display decoders,

multiplexers, keypads, adders, subtractors, ROM, RAM, and dot matrix displays. The last seven

labs of this book are presented in great detail at a somewhat slower or relaxed pace.

If you are concerned about the pace used to present the material in the first five labs, there

are solutions. The Instructor's CD-ROM that comes with this book includes the resources that

accompanied my first book. They include; transparency masters {class notes), all the tutorial

worksheets, and tutorial solutions. This means an instructor has access to class notes and

worksheets for 16 labs of my first book and can use them to present the information found in the

first 5 labs of this book. Another approach would be to use both books. This approach may be

better suited to a two-part digital ^ndamentals course that spans two semesters. Schools that

teach a single semester course will likely find that this book, on its own, with the additional

resources for Labs 1 to 5 will be sufficient.