201_ASP v8.0 potx

201ASP

Mid-Range Family Peripheral

Configuration and Assembly

Programming

Objectives

 At the end of this class you will:

– Understand the basic PICmicro

peripherals and their associated

registers

– Have “HANDS ON” experience

initializing Mid-Range peripherals

– Be able to implement peripherals

not covered here

– Understand interrupts and polling

– Write your own application code

from “scratch”

To get the most from this Class

 Ideally you should be familiar with the

following:

– Assembler programming

– Basic Mid-Range family Instruction set

– Data and Program memory organization

– MPLAB Integrated Development

Environment

– Microchip ICD2 debugger

201ASP Agenda

 Brief review of Mid-Range

Architecture, Instruction Set and

Tools

 Interrupts on the Mid-Range PICmicro

– Interrupts Lab

 Peripheral discussion:

– Input/Output Ports

– Timers

 Timer0

 Timer1

– Timer1 Lab

 Timer2

– Timer2 Lab

201ASP Agenda (cont.)

 Capture / Compare / PWM Module (CCP)

– PWM and Output Compare Labs

 Analog Comparator

 Analog to Digital Converters (ADC)

– ADC Lab

 Addressable Universal Asynchronous &

Synchronous Receiver & Transmitter

(AUSART)

 I2C with the Master Synchronous Serial Port

– I2C Based Temp Sensor Lab

 Wrap-Up and additional questions

Mid-Range Family Basic

Architecture and

Development Tools

Mid-Range PIC Block Diagram

ADC

TIMER0

MUX

ALU

AUSART

MSSP

PERIPHERALS

WORKING

STATUS REGISTER

Pages of

Program

Memory

Banks of Data Memory

INSTRUCTION REGISTER

8-bit value from instruction

14-bits

PROGRAM COUNTER

Program Memory

 Maximum 8K words

– (8K x 14 bits/word)/1

byte = 14Kbytes of memory

 Reset Vector at 0000h

– Program Counter (PC) will

go to this address on

reset

 Interrupt Vector at

0004h

– Program Counter (PC) will

go to this address upon

any Interrupt

Reset Vector

Interrupt Vector

Page 0

Page 1

Page 2

Page 3

0000h

0004h

0005h

07FFh

0800h

0FFFh

1000h

17FFh

1800h

1FFFh

Program Counter (PC) and Stack

 13-bit PC

– PCL ALU result (8-bits)

or OPCODE(11-bits)

– PCH Paging bits

 Updated from PCLATH

 Specifies page in program

memory

 8 Level Deep Stack

– Stores the contents of

the PC

 PUSHES

– CALL/Interrupt

 POPS

– RETURN, RETFIE,RETLW

PCLATH

PCH<12:8> PCL

Stack Level 1

Stack Level 8

Program Memory

PC<12:0>

CALL, RETURN,

RETFIE, RETLW

Data Memory Map

128

Bytes

Shared Shared Shared

Bank 0 Bank1 Bank2 Bank3

000h

01Fh

020h

07Fh

080h

09Fh

0A0h

0FFh

100h

110h

17Fh

180h

190h

1FFh

0EFh 16Fh 1EFh

10Fh 18Fh Special

Function

Registers

SFR SFR

General

Purpose

Registers

General

Purpose

Registers

Special

Function

Registers

General

Purpose

Registers

General

Purpose

Registers

Special Function Registers (SFRs)

PORTB 06h

PORTC 07h

PORTD 08h

PORTE 09h

PCLATH 0Ah

INTCON 0Bh

PIR1 0Ch

PIR2 0Dh

TRISB 86h

TRISC 87h

TRISD 88h

TRISE 89h

PCLATH 8Ah

INTCON 8Bh

PIE1 8Ch

PIE2 8Dh

Bank0 Bank1

 Register File

Concept

 Accessed like any

other register

 Some registers carry

across all banks

(PCLATH, INTCON, etc.)

Status Register

 Contains:

– Arithmetic status of

the ALU

– The RESET status

– Bank select bits for

data memory

RP1 RP0

RP1 0 RP00

0 1

1 0

1 1

BANK0

BANK1

BANK2

BANK3

IRP RP1 RP0 TO PD Z DC C

Indirect Register Bank Select bit:

(used for indirect addressing)

1 = Bank 2,3

0 = Bank 0,1

PIC16 Instruction Set

 35 single word instructions

 All are single cycle except for program branches

Byte Oriented Operations Bit Oriented Operations

addwf f,d

andwf f,d

clrf f

clrw -

comf f,d

decf f,d

decfsz f,d

incf f,d

incfsz f,d

iorwf f,d

movf f,d

movwf f

nop -

rlf f,d

rrf f,d

subwf f,d

swapf swapf f,d

xorwf f,d

Add W and f Add W and f

AND W with f

Clear f Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f Move W to f

No Operation

Rotate Left f through Carry Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f Exclusive OR W with f

bcf f,b

bsf f,b

btfsc f,b

btfss f,b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set Bit Test f, Skip if Set

Literal and Control Operations

addlw k

andlw k

call k

clrwdt -

goto k

iorlw k

movlw k

retfie retfie -

retlw k

return reurn -

sleep -

sublw k

xorlw k

Add literal and W Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W Return with literal in W

Return from Subroutine

Go into standby mode Go into standby mode

Subtract W from literal Subtract W from literal

Exclusive OR literal with W

PICmicro Development

Tools

MPLAB® IDE

 MPLAB® IDE (Integrated Development

Environment)

 Integrates different Microchip and

third party tools

– Code Editor

– Cross Compilers

– Assemblers

– Simulators, In-Circuit

Debuggers, Emulators

– Programmers

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